Patent Assignment
Reel/Frame 018923/0630
CORRECTIVE ASSIGNMENT ON REEL 018711, FRAME 0567
Recorded: 2007-02-15
Received: 2007-02-15
Pages: 9
Assignor
QST HOLDINGS, LLC
Executed: 2006-09-19
Assignee
NVIDIA CORPORATION
2701 SAN TOMAS EXPRESSWAY, SANTA CLARA, CA, 95050, UNITED STATES
Covered Applications
(33)
METHOD FOR ESTIMATING COST WHEN PLACING OPERATIONS WITHIN A MODULO SCHEDULER WHEN SCHEDULING FOR PROCESSORS WITH A LARGE NUMBER OF FUNCTION UNITS OR RECONFIGURABLE DATA PATHS
App. No. 11/473,340
→
INTERNAL SYNCHRONIZATION CONTROL FOR ADAPTIVE INTEGRATED CIRCUITRY
App. No. 10/937,728
→
SYSTEM AND METHOD USING EMBEDDED MICROPROCESSOR AS A NODE IN AN ADAPTABLE COMPUTING MACHINE
App. No. 10/765,556
→
INPUT/OUTPUT CONTROLLER NODE IN AN ADAPTABLE COMPUTING ENVIRONMENT
App. No. 10/719,409
→
RECONFIGURABLE BIT-MANIPULATION NODE
App. No. 10/683,563
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SYSTEM AND METHOD USING EMBEDDED MICROPROCESSOR AS A NODE IN AN ADAPTABLE COMPUTING MACHINE
App. No. 10/673,678
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ASYNCHRONOUS, INDEPENDENT AND MULTIPLE PROCESS SHARED MEMORY SYSTEM IN AN ADAPTIVE COMPUTING ARCHITECTURE
App. No. 10/644,621
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DATA FLOW CONTROL FOR ADAPTIVE INTEGRATED CIRCUITRY
App. No. 10/641,976
→
CACHE FOR INSTRUCTION SET ARCHITECTURE
App. No. 10/628,036
→
CACHE FOR INSTRUCTION SET ARCHITECTURE USING INDEXES TO ACHIEVE COMPRESSION
App. No. 10/628,083
→
INPUT PIPELINE REGISTERS FOR A NODE IN AN ADAPTIVE COMPUTING ENGINE
App. No. 10/626,479
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SYSTEM FOR FREQUENCY-DOMAIN SCALING FOR DISCRETE COSINE TRANSFORM
App. No. 10/612,202
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METHOD AND SYSTEM FOR REDUCING THE TIME-TO-MARKET CONCERNS FOR EMBEDDED SYSTEM DESIGN
App. No. 10/459,859
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PROCESSING ARCHITECTURE FOR A RECONFIGURABLE ARITHMETIC NODE
App. No. 10/443,596
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DATA DISTRIBUTOR IN A COMPUTATION UNIT FORWARDING NETWORK DATA TO SELECT COMPONENTS IN RESPECTIVE COMMUNICATION METHOD TYPE
App. No. 10/443,554
→
RECONFIGURABLE FILTER NODE FOR AN ADAPTIVE COMPUTING MACHINE
App. No. 10/386,896
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ARITHMETIC NODE INCLUDING GENERAL DIGITAL SIGNAL PROCESSING FUNCTIONS FOR AN ADAPTIVE COMPUTING MACHINE
App. No. 10/367,188
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SYSTEM FOR HARDWARE ASSISTED FREE LIST MANAGEMENT
App. No. 10/356,671
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DIGITAL PROCESSING ARCHITECTURE USING COMPILED DATAFLOW DEFINITION
App. No. 10/342,888
→
METHOD AND SYSTEM FOR PROVIDING AN EXCITATION-PATTERN BASED AUDIO CODING SCHEME
App. No. 10/340,060
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SECURE STORAGE OF PROGRAM CODE FOR AN EMBEDDED SYSTEM
App. No. 10/286,633
→
Retargetable compiler for multiple and different hardware platforms
App. No. 10/264,485
→
METHOD AND SYSTEM FOR IMPLEMENTING A LOW-COMPLEXITY SCHEME IN COLOR CONVERSION AND DOWN-SAMPLING OF IMAGE CODECS
App. No. 10/263,941
→
METHOD AND APPARATUS FOR WATERMARKING BINARY COMPUTER CODE WITH MODIFIED COMPILER OPTIMIZATIONS
App. No. 10/223,205
→
Method and apparatus for watermarking binary computer code
App. No. 10/223,256
→
CONSUMER PRODUCT DISTRIBUTION IN THE EMBEDDED SYSTEM MARKET
App. No. 10/199,923
→
METHOD AND SYSTEM FOR A FLOATING POINT MULTIPLY-ACCUMULATOR
App. No. 10/192,391
→
METHOD AND SYSTEM FOR REAL-TIME MULTITASKING
App. No. 10/189,791
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METHOD FOR ESTIMATING COST WHEN PLACING OPERATIONS WITHIN A MODULO SCHEDULER WHEN SCHEDULING FOR PROCESSORS WITH A LARGE NUMBER OF FUNCTION UNITS OR RECONFIGURABLE DATA PATHS
App. No. 10/160,665
→
SCRIPTING LANGUAGE FOR PROCESSING TYPED STRUCTURED DATA
App. No. 10/136,055
→
IC FOR UNIVERSAL COMPUTING WITH NEAR ZERO PROGRAMMING COMPLEXITY
App. No. 10/029,502
→
METHOD AND SYSTEM FOR INCREASING AVAILABILITY AND PROXIMITY OF BASE STATIONS FOR CELLULAR COMMUNICATIONS VIA MOBILE BASE STATIONS
App. No. 10/010,596
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PREDICTIVE RESOURCE ALLOCATION IN COMPUTING SYSTEMS
App. No. 09/974,521
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