IP Library Granted Patent US 7,225,279
Granted Patent B2
US 7,225,279 · App. 10/443,554 · Granted May 29, 2007

Data distributor in a computation unit forwarding network data to select components in respective communication method type

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Quick Facts
Patent No.
US 7,225,279
App. No.
10/443,554
Granted
May 29, 2007
Kind
B2
Abstract

A data distributor in a computational unit of an integrated circuit is enclosed. The data distributor receives data from a network and distributes the data to a plurality of components within the computational unit. The data distributor includes an input mechanism for receiving the data from the network, and distributes the data to a selected component of the plurality of components, a control mechanism responsive to a control signal for distributing the data to the selected component using a data distribution selected between a look-up table-based memory write and a point-to-point distribution with acknowledgement. The plurality of components comprises a Peek/Poke Module, an Execution Unit, a DMA Engine, and a Hardware Task Manager Message Generator. The selected data distribution type may comprise using an output port number or a direct-memory address transfer or an interrupt to distribute the data.

Claims (37)

1. A data distributor in a computational unit of an integrated circuit, wherein the data distributor receives data from a network and distributes the data to a plurality of components within the computational unit, the data distributor comprising

an input mechanism for receiving the data from the network at the data distributor in the computational unit;

a distribution mechanism responsive to a control signal for distributing the data to a selected component of the plurality of components, wherein the data is distributed as it is received from the network; and

a control mechanism responsive to a control signal for distributing the data to the selected component using a selected data distribution type of a plurality of data distribution types, the plurality of data distribution types comprising a look-up table-based memory write and a point-to-point distribution with acknowledgement.

2. The data distributor of claim 1 , wherein the selected component includes a register configured to store the distributed data.

3. The data distributor of claim 1 , wherein the selected component includes a memory configured to store the distributed data.

4. The data distributor of claim 1 , wherein any contentions between the input mechanism and the selected component are resolved in favor of the input mechanism.

5. The data distributor of claim 1 , wherein the selected data distribution type further comprises using an output port number to distribute the data.

6. The data distributor of claim 1 , wherein the selected data distribution type further comprises using a direct-memory address transfer to distribute the data.

7. The data distributor of claim 1 , wherein the selected data distribution type further comprises using an interrupt to distribute the data.

8. The data distributor of claim 1 , wherein the input mechanism includes a pipeline register.

9. The data distribution of claim 1 , further comprising an output register coupled to the network; and an arbiter mechanism for arbitrating priority of the requests from the plurality of components.

10. The data distributor of claim 9 , wherein the plurality of components comprises a Peek/Poke Module.

11. The data distributor of claim 9 , wherein the plurality of components comprise an Execution Unit.

12. The data distributor of claim 9 , wherein the plurality of components comprise a DMA Engine.

13. The data distributor of claim 9 , wherein the plurality of components comprise a Hardware Task Manager Message Generator.

14. The data distributor of claim 1 , wherein data is received from a plurality of reconfigurable nodes, and wherein the data distributor is configured to distribute the data from the reconfigurable nodes based on information in the data.

15. A method for distributing data in a computational unit of an integrated circuit, the method comprising

receiving data from a network couplable to the integrated circuit;

selecting a data distribution type of a plurality of data distribution types, the plurality of data distribution types comprising a look-up table-based memory write and a point-to-point distribution with acknowledgement; and

distributing the data to a selected component of a plurality of components within the computational unit according to a control signal for distributing the data to the selected component and according to a control signal for distributing the data using the selected data distribution type.

16. The method of claim 15 , wherein the selected component includes a register.

17. The method of claim 15 , wherein the selected component includes a memory.

18. The method of claim 15 , wherein the selected data distribution type further comprises using an output port number to distribute the data.

19. The method of claim 15 , wherein the selected data distribution type further comprises using a direct-memory address transfer to distribute the data.

20. The method of claim 15 , wherein the selected data distribution type further comprises using an interrupt to distribute the data.

21. The method of claim 15 , wherein the data is received by an input mechanism comprising a pipeline register.

22. The method of claim 15 , further comprising:

arbitrating among the plurality of components to select output data to transfer to the network; and

outputting the selected data to the network.

23. The method of claim 22 , further comprising sending data to an output register coupled to the network; and prioritizing requests from the plurality of components.

24. The method of claim 22 , wherein one of the plurality of components comprise a Peek/Poke Module.

25. The method of claim 22 , wherein one of the plurality of components compromise an Execution Unit.

26. The method of claim 22 , wherein one of the plurality of components comprise a DMA Engine.

27. The method of claim 22 , wherein one of the plurality of components comprise a Hardware Task Manager Message Generator.

28. The method of claim 15 , wherein any contentions between the input mechanism and the selected component are resolved in favor of the input mechanism.

29. The method of claim 15 , wherein data is received from a plurality of reconfigurable nodes, wherein the data distributor is configured to distribute the data from the reconfigurable nodes based on information in the data.

Assignments (5)
CORRECTIVE ASSIGNMENT ON REEL 018711, FRAME 0567 Recorded Feb 15, 2007
From: QST HOLDINGS, LLC
To: NVIDIA CORPORATION
Reel/Frame 018923/0630 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2007
From: QST HOLDINGS, L.L.C.
To: NVIDIA CORPORATION
Reel/Frame 018711/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2006
From: TECHFARM VENTURES MANAGEMENT, LLC
To: QST HOLDINGS, LLC
Reel/Frame 018224/0634 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2006
From: QUICKSILVER TECHNOLOGY, INC.
To: TECHFARM VENTURES MANAGEMENT, LLC
Reel/Frame 018194/0515 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2003
From: SCHEUERMANN, W. JAMES; HOGENAUER, EUGENE B.
To: QUICKSILVER TECHNOLOGY, INC.
Reel/Frame 014505/0099 →