Patent Assignment
Reel/Frame 018224/0634
Assignment of Assignor's Interest
Recorded: 2006-09-05
Received: 2006-09-05
Pages: 20
Assignor
TECHFARM VENTURES MANAGEMENT, LLC
Executed: 2006-08-31
Assignee
QST HOLDINGS, LLC
200 WEST EVELYN AVENUE, SUITE 100, MOUNTAIN VIEW, CA, 94041, UNITED STATES
Covered Properties
(38)
Method for Estimating Cost When Placing Operations Within a Modulo Scheduler When Scheduling for Processors with a Large Number of Function Units or Reconfigurable Data Paths
Application:
11/473,340 →
Processor for Video Data
Application:
11/125,852 →
Processor for Video Data Encoding/Decoding
Application:
11/125,854 →
Internal Synchronization Control for Adaptive Integrated Circuitry
Application:
10/937,728 →
Equalization for Dmt and Ofdm Communication Systems
Application:
10/889,530 →
Ultra-Drowsy Circuit
Application:
10/881,850 →
Viterbi Decoder with Survivor Bits Stored to Support Look-Ahead Addressing
Application:
10/784,484 →
System and Method Using Embedded Microprocessor as a Node in an Adaptable Computing Machine
Application:
10/765,556 →
Input/Output Controller Node in an Adaptable Computing Environment
Application:
10/719,409 →
Reconfigurable Bit-Manipulation Node
Application:
10/683,563 →
System and Method Using Embedded Microprocessor as a Node in an Adaptable Computing Machine
Application:
10/673,678 →
Asynchronous, Independent and Multiple Process Shared Memory System in an Adaptive Computing Architecture
Application:
10/644,621 →
Data Flow Control for Adaptive Integrated Circuitry
Application:
10/641,976 →
Cache for Instruction Set Architecture Using Indexes to Achieve Compression
Application:
10/628,083 →
Cache for Instruction Set Architecture
Application:
10/628,036 →
Input Pipeline Registers for a Node in an Adaptive Computing Engine
Application:
10/626,479 →
System for Frequency-Domain Scaling for Discrete Cosine Transform
Application:
10/612,202 →
Method and System for Reducing the Time-to-Market Concerns for Embedded System Design
Application:
10/459,859 →
Processing Architecture for a Reconfigurable Arithmetic Node
Application:
10/443,596 →
Data Distributor in a Computation Unit Forwarding Network Data to Select Components in Respective Communication Method Type
Application:
10/443,554 →
Reconfigurable Filter Node for an Adaptive Computing Machine
Application:
10/386,896 →
Arithmetic Node Including General Digital Signal Processing Functions for an Adaptive Computing Machine
Application:
10/367,188 →
System for Hardware Assisted Free List Management
Application:
10/356,671 →
Digital Processing Architecture Using Compiled Dataflow Definition
Application:
10/342,888 →
Method and System for Providing an Excitation-Pattern Based Audio Coding Scheme
Application:
10/340,060 →
Secure Storage of Program Code for an Embedded System
Application:
10/286,633 →
Retargetable compiler for multiple and different hardware platforms
Application:
10/264,485 →
Method and System for Implementing a Low-Complexity Scheme in Color Conversion and Down-Sampling of Image Codecs
Application:
10/263,941 →
Method and Apparatus for Watermarking Binary Computer Code with Modified Compiler Optimizations
Application:
10/223,205 →
Method and apparatus for watermarking binary computer code
Application:
10/223,256 →
Consumer Product Distribution in the Embedded System Market
Application:
10/199,923 →
Method and System for a Floating Point Multiply-Accumulator
Application:
10/192,391 →
Method and System for Real-Time Multitasking
Application:
10/189,791 →
Scripting Language for Processing Typed Structured Data
Application:
10/136,055 →
Ic for Universal Computing with Near Zero Programming Complexity
Application:
10/029,502 →
Method and System for Increasing Availability and Proximity of Base Stations for Cellular Communications via Mobile Base Stations
Application:
10/010,596 →
Predictive Resource Allocation in Computing Systems
Application:
09/974,521 →
High Performance Memory Efficient Variable-Length Coding Decoder
Application:
09/916,161 →