Processor for video data encoding/decoding
View Patent ↗A video processor uses attributes of video data to perform encoding and decoding. Some embodiments dynamically configure the processor via a sequence of instructions, where the instructions include information on the attributes of the current video data. Some embodiments include a dynamically configurable adder array that computes difference functions thereby generating error vectors. Some embodiments include a dynamically configurable adder array that computes filtering functions applied to the video data, e.g. interpolation or decimation of the incoming video prior to motion detection. Some embodiments of the invention provide dynamically configurable hardware searches, for example, for detecting motion. Some embodiments of the invention are implemented using an adaptive computing machines (ACMs). An ACM includes a plurality of heterogeneous computational elements, each coupled to an interconnection network.
1. A system for processing video data, comprising:
a reconfigurable digital video processor including an array of adders configured to perform motion estimation on a sequence of frames by performing a plurality of sum of absolute differences (SAD) operations, wherein performing motion estimation includes comparing a block of picture elements (PELs) associated with a current frame with a block of PELs associated with a frame before the current frame or with a block of PELs associated with a frame subsequent to the current frame, wherein the reconfigurable digital video processor includes heterogeneous processing nodes connected by a matrix interconnect network; and
a control processor configured to provide instructions to the reconfigurable digital video processor that dynamically configure the heterogeneous processing nodes and the matrix interconnect network included in the reconfigurable digital video processor to receive input video data associated with a first format and to generate output video data associated with a second format,
wherein the instructions include information related to both the first format and a first resolution of the input video data as well as the second format and a second resolution of the output video data, and
wherein the instructions further include degree of compression information.
2. The system of claim 1 , wherein the control processor includes a decoder configured to decode instructions, for determining therefrom the first format associated with the input video data.
3. The system of claim 1 , wherein the array of adders includes:
an interpolation filter configured to receive the input video data, to generate interpolated PELs from the input video data, and to generate preprocessed video that includes PELs from the input video data and interpolated PELs where the interpolated PELs are generated by the array of adders; and
an encoder/decoder configured to generate the output video from the preprocessed video,
wherein the interpolation filter is programmable based on the first format associated with the input video data and based on a resolution of the input video data.
4. The system of claim 3 , wherein fractional PEL processing is performed.
5. The system of claim 4 , wherein an oversized reference block is used.
6. The system of claim 4 , wherein a minimum number of PELs consistent with a desired range is used.
7. The system of claim 1 where the array of adders forms a sum of absolute differences (SAD) computer.
8. The system of claim 1 , where the input video data has a format including one or more properties of MPEG-2, MPEG-4, Windows media video (WMV), or X.264.
9. The system of claim 1 , where the output video data has a predetermined resolution.
10. The system of claim 1 , where the processor is implemented based on an adaptive computing machine (ACM).