Patent Assignment
Reel/Frame 018954/0251
Assignment of Assignor's Interest
Recorded: 2007-03-02
Pages: 3
Assignee
VIA TECHNOLOGIES, INC.
8F, 535, CHUNG-CHENG ROAD, HSIN-TIEN, TAIPEI, 231, TAIWAN
Covered Property
(1)
Microprocessor and Method for Utilizing Disparity Between Bus Clock and Core Clock Frequencies to Prioritize Cache Line Fill Bus Access Requests
Related Assignments
(1)
Other recorded transfers of the patent in this record — the chain of ownership.