Patent Assignment
Reel/Frame 019069/0324
ASSIGNMENT OF ASSIGNOR'S INTEREST
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Applications
(29)
A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-MICRON FLASH MEMORY SEMICONDUCTOR DEVICE
App. No. 10/244,129
→
NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN FABRICATION OF SONOS FLASH MEMORY
App. No. 10/158,044
→
PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
App. No. 10/091,767
→
SWITCHED-CAPACITOR CONTROLLER TO CONTROL THE RISE TIMES OF ON-CHIP GENERATED HIGH VOLTAGES
App. No. 10/015,033
→
FORMATION OF STI (SHALLOW TRENCH ISOLATION) STRUCTURES WITHIN CORE AND PERIPHERY AREAS OF FLASH MEMORY DEVICE
App. No. 09/969,573
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NITRIDE BARRIER LAYER FOR PROTECTION OF ONO STRUCTURE FROM TOP OXIDE LOSS IN A FABRICATION OF SONOS FLASH MEMORY
App. No. 09/966,702
→
OXIDE/NITRIDE OR OXIDE/NITRIDE/OXIDE THICKNESS MEASUREMENT USING SCATTEROMETRY
App. No. 09/904,089
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ECHOGENIC MEDICAL DEVICE
App. No. 09/878,159
→
METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
App. No. 09/875,056
→
METHOD AND SYSTEM FOR QUALIFYING AN ONO LAYER IN A SEMICONDUCTOR DEVICE
App. No. 09/875,073
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THRESHOLD VOLTAGE COMPACTING FOR NON-VOLATILE SEMICONDUCTOR MEMORY DESIGNS
App. No. 09/851,773
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METHOD AND SYSTEM FOR REDUCING THINNING OF FIELD ISOLATION STRUCTURES IN A FLASH MEMORY DEVICE
App. No. 09/844,692
→
ACCURATE VERIFY APPARATUS AND METHOD FOR NOR FLASH MEMORY CELLS IN THE PRESENCE OF HIGH COLUMN LEAKAGE
App. No. 09/842,288
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SYSTEM AND METHOD FOR ERASE TEST OF INTEGRATED CIRCUIT DEVICE HAVING NON-HOMOGENEOUSLY SIZED SECTORS
App. No. 09/836,065
→
FORMATION OF NON-VOLATILE MEMORY DEVICE COMPRISED OF AN ARRAY OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURES
App. No. 09/817,628
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HIGH VOLTAGE OXIDATION METHOD FOR HIGHLY RELIABLE FLASH MEMORY DEVICES
App. No. 09/803,400
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STAIRCASE PROGRAM VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/794,482
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Descending staircase read technique for a multilevel cell NAND flash memory device
App. No. 09/794,485
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CONFIGURE REGISTERS AND LOADS TO TAILOR A MULTI-LEVEL CELL FLASH DESIGN
App. No. 09/794,479
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ADDRESS BROADCASTING TO A PAGED MEMORY DEVICE TO ELIMINATE ACCESS LATENCY PENALTY
App. No. 09/794,478
→
ASCENDING STAIRCASE READ TECHNIQUE FOR A MULTILEVEL CELL NAND FLASH MEMORY DEVICE
App. No. 09/794,480
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METHOD OF FORMING A VOID-FREE INTERLAYER DIELECTRIC (ILD0) FOR 0.18-UM FLASH MEMORY TECHNOLOGY AND SEMICONDUCTOR DEVICE THEREBY FORMED
App. No. 09/788,045
→
PIGGYBACK PROGRAMMING USING VOLTAGE CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,821
→
PROGRAM RECONNAISSANCE TO ELIMINATE VARIATIONS IN VT DISTRIBUTIONS OF MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,864
→
PIGGYBACK PROGRAMMING USING AN EXTENDED FIRST PULSE FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,794
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CONCURRENT PROGRAM RECONNAISSANCE WITH PIGGYBACK PULSES FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,764
→
PIGGYBACK PROGRAMMING USING GRADUATED STEPS FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,225
→
PIGGYBACK PROGRAMMING USING TIMING CONTROL FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,792
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PIGGYBACK PROGRAMMING WITH STAIRCASE VERIFY FOR MULTI-LEVEL CELL FLASH MEMORY DESIGNS
App. No. 09/779,884
→