Assignment of Assignor's Interest

Recorded: 2007-04-05 Pages: 7

Assignors

DARBINYAN, KAREN

Executed: 2007-04-03

CHUKHAJYAN, HAYK

Executed: 2007-04-05

HARUTYUNYAN, ALBERT

Executed: 2007-04-05

ZORIAN, YERVANT

Executed: 2007-04-05

Assignee

VIRAGE LOGIC CORP.

47100 BAYSIDE PARKWAY, FREMONT, CALIFORNIA, 94538

Covered Property (1)

System and Method for Verifying Ip Integrity in System-on-Chip (Soc) Design

Patent: 7,673,264 →

Application: 11/732,900 →

Related Assignments (1)

Other recorded transfers of the patent in this record — the chain of ownership.