IP Library › Assignment 019396/0521
Patent Assignment
Reel/Frame 019396/0521

Assignment of Assignor's Interest

Recorded: 2007-06-07 Pages: 3
Assignor
JING, TAO
Executed: 2007-06-06
Assignee
INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD, SAN JOSE, CALIFORNIA, 95138
Covered Property (1)
Input Clock Detection Circuit for Powering Down a Pll-Based System
Patent: 7,567,100 →
Application: 11/694,861 →
Publication: US 2008/0238508
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Security Agreement Apr 5, 2017
From: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; MAGNUM SEMICONDUCTOR, INC.; ENDWAVE CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 042166/0431 →
Release of Security Interest Mar 29, 2019
From: JPMORGAN CHASE BANK, N.A.
To: INTEGRATED DEVICE TECHNOLOGY, INC.; GIGPEAK, INC.; CHIPX, INCORPORATED; ENDWAVE CORPORATION
Reel/Frame 048746/0001 →