IP Library Assignment 020197/0854
Patent Assignment
Reel/Frame 020197/0854

Assignment of Assignor's Interest

Recorded: 2007-12-05 Pages: 5
Assignors
EILERT, SEAN S.
Executed: 2006-12-19
ROZMAN, RODNEY R.
Executed: 2007-01-02
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95052
Covered Property (1)
High Speed Fanned Out System Architecture and Input/Output Circuits for Non-Volatile Memory
Patent: 7,567,471 →
Application: 11/645,043 →
Publication: US 2008/0151648
Related Assignments (2)
Other recorded transfers of the patent in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 20, 2007
From: QAWAMI, SHEKOUFEH; HINTON, GLENN
To: INTEL CORPORATION
Reel/Frame 020278/0029 →
Assignment of Assignor's Interest Feb 10, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062702/0048 →