Patent Assignment
Reel/Frame 062702/0048
Assignment of Assignor's Interest
Recorded: 2023-02-10
Pages: 48
Assignor
INTEL CORPORATION
Executed: 2021-12-29
Assignee
SK HYNIX NAND PRODUCT SOLUTIONS CORP.
3101 N. 1ST STREET, SAN JOSE, CALIFORNIA, 95134
Covered Properties
(95)
High Speed Fanned Out System Architecture and Input/Output Circuits for Non-Volatile Memory
Techniques to Perform Power Fail-Safe Caching Without Atomic Metadata
Method and System to Perform Caching Based on File-Level Heuristics
Dual-Scope Directory for a Non-Volatile Memory Storage System
Hybrid Memory Architectures
Apparatus and Method for Accessing a Secure Partition in Non-Volatile Storage by a Host System Enabled After the System Exits a First Instance of a Secure Mode
Method and System of Adapting Communication Links to Link Conditions on a Platform
Storage Drive Based Antimalware Methods and Apparatuses
Apparatus, System, and Method for Decoding Linear Block Codes in a Memory Controller
Apparatus, System, and Method for Generating and Decoding a Longer Linear Block Codeword Using a Shorter Block Length
Method, Apparatus and System for Determining an Identifier of a Volume of Memory
Patent:
8,463,948 →
Application:
13/175,721 →
Apparatus, System, and Method for Improving Read Endurance for a Non-Volatile Memory
Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection
Techniques to Perform Power Fail-Safe Caching Without Atomic Metadata
Alternate Control Settings
Driver-Assisted Base Address Register Mapping
Configuration Information Backup in Memory Systems
Method, Apparatus and System for Handling Data Faults
Endurance Aware Error-Correcting Code (Ecc) Protection for Non-Volatile Memories
Persistent Log Operations for Non-Volatile Memory
Serial Storage Protocol Compatible Frame Conversion, at Least in Part Being Compatible with Sata and One Packet Being Compatible with Pcie Protocol
Flexible Wear Management for Non-Volatile Memory
Scaling Factors for Hard Decision Reads of Codewords Distributed Across Die
Method and Apparatus for Controlling a Storage Device
Techniques for Error Correction of Encoded Data
Method, System and Apparatus for Providing Access to Error Correction Information
In-Place Change Between Transient and Persistent State for Data Structures on Non-Volatile Memory
Error Detection and Correction Apparatus and Method
Single-Bit First Error Correction
Selective Provision of Error Correction for Memory
Apparatus and Method to Provide Near Zero Power Devslp in Sata Drives
Constructing Persistent File System from Scattered Persistent Regions
Erase Management in Memory Systems
Techniques for Identifying Read/Write Access Collisions for a Storage Medium
Techniques for Moving Data between a Network Input/Output Device and a Storage Device
Adaptive Configuration of Non-Volatile Memory
Nonvolatile Memory Wear Management
Storage of Codeword Portions
Host Controlled Hybrid Storage Device
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy Having Different Operating Modes
Updating Variable Nodes Associated with an Iterative Decoder
High-Performance Storage Structures and Systems Featuring Multiple Non-Volatile Memories
Maintaining at Least One Journal and/or at Least One Data Structure by Circuitry
Memory Controller with Distribution Transformer
Use of Error Correction Pointers to Handle Errors in Memory
Techniques to Perform Power Fail-Safe Caching Without Atomic Metadata
Protected Device Management
Hybrid Memory Architectures
Flexible Wear Management for Non-Volatile Memory
Memory Latency Management
In-Place Change Between Transient and Persistent State for Data Structures on Non-Volatile Memory
Configuration Information Backup in Memory Systems
Adaptive Configuration of Non-Volatile Memory
Host Controlled Hybrid Storage Device
Devices, System, and Methods for Implementing Alternate Control Settings
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy Having Different Operating Modes
Determination of Demarcation Voltage for Managing Drift in Non-Volatile Memory Devices
Patent:
9,691,492 →
Application:
15/280,669 →
Techniques to Perform Power Fail-Safe Caching Without Atomic Metadata
Configuration Information Backup in Memory Systems
Technologies for Prioritizing Execution of Storage Commands
Logical Block Address to Physical Block Address (L2P) Table Compression
Self-Configuring Error Control Coding
Key-Value Compaction
Key-Value Deduplication
Logical Band-Based Key-Value Storage Structure
Selective Data Flush in a Storage Drive
Solid State Drive Physical Block Revectoring to Improve Cluster Failure Rates
Memory Latency Management
Method of Dirty Cache Line Eviction
Ssd with Persistent Dram Region for Metadata
Update-Insert for Key-Value Storage Interface
Nvdimm Emulation Using a Host Memory Buffer
Checkpointing for Dram-Less Ssd
Adaptive Configuration of Non-Volatile Memory
Apparatus and Method for Implementing a Multi-Level Memory Hierarchy Having Different Operating Modes
Temperature Management in Open-Channel Memory Devices
Method to Improve Mixed Workload Performance on Storage Devices That Use Cached Operations
Ssd Boot Based on Prioritized Endurance Groups
Application:
16/181,980 →
Publication:
US 2019/0073302
Ssd Temperature Control Technique
Method and Apparatus for Journal Aware Cache Management
Storage System That Provides Protection Levels at Stored Data Item Granularity
Efficient Metadata Storage for a Non-Volatile Storage Device
Techniques to Perform Power Fail-Safe Caching Without Atomic Metadata
Application:
16/405,918 →
Publication:
US 2020/0034304
Techniques for Moving Data between a Network Input/Output Device and a Storage Device
Application:
16/418,405 →
Publication:
US 2019/0272124
Non-Uniform Iteration-Dependent Min-Sum Scaling Factors for Improved Performance of Spatially-Coupled Ldpc Codes
Low Density Parity Check (Ldpc) Decoder Architecture with Check Node Storage (Cns) or Bounded Circulant
Direct Map Memory Extension for Storage Class Memory
Undo and Redo of Soft Post Package Repair
Maintaining Storage Namespace Identifiers for Live Virtualized Execution Environment Migration
Solid State Drive with External Software Execution to Effect Internal Solid-State Drive Operations
Adaptive Write Acknowledgment for Storage Devices
Communication of Data Relocation Information by Storage Device to Host to Improve System Performance
Configuring Parameters of Non-Volatile Memory Target Subsystems for Workload Request Quality of Service
Storage Device with Client Reconfigurable Protocol
Memory Device Firmware Update and Activation Without Memory Access Quiescence
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Dec 5, 2007
From: EILERT, SEAN S.; ROZMAN, RODNEY R.
To: INTEL CORPORATION
Reel/Frame 020197/0854 →
Assignment of Assignor's Interest
Dec 20, 2007
From: QAWAMI, SHEKOUFEH; HINTON, GLENN
To: INTEL CORPORATION
Reel/Frame 020278/0029 →
Assignment of Assignor's Interest
Apr 29, 2009
From: TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 022611/0532 →
Assignment of Assignor's Interest
Jun 5, 2009
From: TRIKA, SANJEEV N.; HUFFMAN, AMBER D.; BOYD, JAMES A.; HADY, FRANK T.
To: INTEL CORPORATION
Reel/Frame 022788/0672 →
Assignment of Assignor's Interest
Sep 17, 2009
From: VOGAN, ANDREW
To: INTEL CORPORATION
Reel/Frame 023248/0641 →
Assignment of Assignor's Interest
Jul 6, 2010
From: CHINNASWAMY, KUMAR K.; OSBORNE, RANDY B.; PETER, ERIK W.
To: INTEL CORPORATION
Reel/Frame 024641/0060 →
Assignment of Assignor's Interest
Aug 6, 2010
From: SWANSON, ROBERT C.; BULUSU, MALLIK; ZIMMER, VINCENT J.
To: INTEL CORPORATION
Reel/Frame 024803/0755 →
Assignment of Assignor's Interest
Oct 29, 2010
From: IYER, VENKATRAMAN; KUMAR, ARVIND; CHAUDHURI, SANTANU; JUE, DARREN S.
To: INTEL CORPORATION
Reel/Frame 025219/0388 →
Assignment of Assignor's Interest
Mar 11, 2011
From: SAXENA, PARITOSH; TRIANTAFILLOU, NICHOLAS D.; THADIKARAN, PAUL J.; SCOTT-NASH, MARK E.
To: INTEL CORPORATION
Reel/Frame 025941/0110 →
Assignment of Assignor's Interest
May 18, 2011
From: KWOK, ZION S.; NELSON, SCOTT
To: INTEL CORPORATION
Reel/Frame 026302/0757 →
Assignment of Assignor's Interest
Jul 20, 2011
From: MOTWANI, RAVI H.
To: INTEL CORPORATION
Reel/Frame 026621/0331 →
Assignment of Assignor's Interest
Aug 19, 2011
From: QAWAMI, SHEKOUFEH; FABER, ROBERT W.
To: INTEL CORPORATION
Reel/Frame 026780/0101 →
Assignment of Assignor's Interest
Feb 1, 2012
From: BELGAL, HANMANT P.; WU, NING; RUBY, PAUL D.; VOGAN, ANDREW
To: INTEL CORPORATION
Reel/Frame 027631/0684 →
Assignment of Assignor's Interest
May 24, 2012
From: SCHAEFER, ANDRE; GRIES, MATTHIAS
To: INTEL CORPORATION
Reel/Frame 028268/0039 →
Assignment of Assignor's Interest
Aug 31, 2012
From: WALKER, JULIE M.; RIVERS, DOYLE
To: INTEL CORPORATION
Reel/Frame 028882/0248 →
Assignment of Assignor's Interest
Sep 13, 2012
From: FOONG, ANNIE; SETO, PAK-LUNG
To: INTEL CORPORATION
Reel/Frame 028952/0885 →
Assignment of Assignor's Interest
Sep 27, 2012
From: WU, NING; FRICKEY, ROBERT E.; BELGAL, HANMANT P.; GUO, XIN
To: INTEL CORPORATION
Reel/Frame 029036/0582 →
Assignment of Assignor's Interest
Sep 16, 2016
From: TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 039769/0630 →