IP Library Granted Patent US 9,015,404
Granted Patent B2
US 9,015,404 · App. 13/630,548 · Granted Apr 21, 2015

Persistent log operations for non-volatile memory

Inventors: Ferad Zyulkyarov (Barcelona, ES); Qiong Cai (Barcelona, ES)
Assignee: Intel Corporation
G06F11/1471
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Quick Facts
Patent No.
US 9,015,404
App. No.
13/630,548
Granted
Apr 21, 2015
Kind
B2
Abstract

In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.

Claims (36)

1. A method comprising:

performing a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM), the information including a current value of a variable contained in the NVM;

performing a second delayed persistence operation to store information in the variable;

performing a third delayed persistence operation to store information in the NVM that indicates the log is cleared; and

performing a flush operation to commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.

2. The method of claim 1 , wherein the information stored by the first delayed persistence operation further includes an address of the variable.

3. The method of claim 1 , wherein the information stored by the third delayed persistence operation is stored in a variable contained in the NVM that indicates a next entry in the log.

4. The method of claim 1 , wherein the information stored by the third delayed persistence operation is stored in a variable contained in the NVM that indicates a number of entries in the log.

5. The method of claim 1 , wherein the information stored by the third delayed persistence operation includes a flag that indicates whether the log is cleared.

6. The method of claim 1 , wherein the at least one of the first, second, or third delayed persistence operation includes an executable instruction that is executable by processing logic.

7. The method of claim 6 , wherein the instruction is executed to perform at least one of the first, second, or third delayed persistence operations.

8. One or more tangible non-transitory computer-readable mediums storing one or more executable instructions for execution by processing logic, the one or more executable instructions including:

one or more executable instructions for storing information in a log contained in a non-volatile memory (NVM) using a first delayed persistence operation, the information including a current value of a variable contained in the NVM;

one or more executable instructions for storing information in the variable using a second delayed persistence operation;

one or more executable instructions for storing information in the NVM that indicates the log is cleared using a third delayed persistence operation; and

one or more executable instructions for committing outstanding information to the NVM, the outstanding information including information associated with at least one of the first, second, or third delayed persistence operations.

9. The medium of claim 8 , wherein the information stored by the first delayed persistence operation further includes an address of the variable.

10. The medium of claim 8 , wherein the information stored by the third delayed persistence operation is stored in a variable contained in the NVM that indicates a next entry in the log.

11. The medium of claim 8 , wherein the information stored by the third delayed persistence operation is stored in a variable contained in the NVM that indicates a number of entries in the log.

12. The medium of claim 8 , wherein the further comprising:

one or more instructions for determining that the log is not cleared;

one or more instructions for acquiring the information stored by the second delayed persistence operation from the log; and

one or more instructions for restoring information contained in the variable based on the acquired information.

13. The medium of claim 12 , wherein the information in the variable is restored by using a delayed persistence operation that writes the acquired information to the variable.

14. A system comprising:

processing logic for:

performing a first operation that stores information in a log contained in a non-volatile memory (NVM) using delayed persistence operation, the information including a current value of a storage location contained in the NVM;

performing a second operation that stores information in the storage location using delayed persistence;

performing a third operation that stores information in the NVM that indicates the log is cleared using delayed persistence; and

committing outstanding information to the NVM, the outstanding information including information associated with at least one of the first, second, or third operations.

15. The system of claim 14 , wherein the information stored by the first operation further includes an address of the variable.

16. The system of claim 14 , wherein the information stored by the third operation is stored in a variable contained in the NVM that indicates a next entry in the log.

17. The system of claim 14 , wherein the information stored by the third operation is stored in a variable contained in the NVM that indicates a number of entries in the log.

18. The system of claim 14 , wherein the information stored by the third operation includes a flag that indicates whether the log is cleared.

19. The system of claim 14 , wherein the at least one of the first, second, or third delayed operations includes an executable instruction that is executable by processing logic.

20. The system of claim 19 , wherein the instruction is executed to perform at least one of the first, second, or third operations.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062702/0048 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2012
From: ZYULKYAROV, FERAD; CAI, QIONG
To: INTEL CORPORATION
Reel/Frame 029052/0633 →
Continuity (1)
Related Publication 20140095766A1 · Apr 3, 2014