IP Library Granted Patent US 10,872,041
Granted Patent B2
US 10,872,041 · App. 16/211,157 · Granted Dec 22, 2020

Method and apparatus for journal aware cache management

Inventors: Madhurima Ray (Philadelphia, PA); Sanjeev N. Trika (Portland, OR)
Assignee: Intel Corporation
G06F12/121G06F12/0804G06F12/0868G06F12/0895G06F2212/1044
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Quick Facts
Patent No.
US 10,872,041
App. No.
16/211,157
Granted
Dec 22, 2020
Kind
B2
Abstract

An intelligent journal-aware caching manager for journaled data is provided. The caching manager ensures that data is not duplicated in a write-ahead-log (“journal”) and volatile cache memory (“cache”). The caching manager maintains first-in-first-out (“FIFO”) policy for the journal as needed and includes an alternate caching policy for non-journaled data.

Claims (25)

1. An apparatus comprising:

a journal to store a key value pair to be written to a storage device;

a cache to store the key value pair read from the storage device; and

journal-aware cache logic to evict the key value pair from the cache when the key value pair is written to the journal and to insert the key value pair in the cache when the key value pair is evicted from the journal such that the key value pair is stored in one of the cache or the journal to ensure the key value pair is not duplicated in the journal and the cache, the journal-aware cache logic comprises a least recently used list, each entry in the least recently used list has a pointer to a cache entry in the cache or to a write-ahead-log entry in the journal.

2. The apparatus of claim 1 , wherein the key value pair stored in the journal to be written to the storage device in first-in-first-out order.

3. The apparatus of claim 1 , wherein the journal is a pseudo non-volatile memory in the storage device.

4. The apparatus of claim 1 , wherein the journal is a non-volatile memory and the cache is a volatile memory.

5. The apparatus of claim 4 , wherein the non-volatile memory is a byte addressable write-in-place memory.

6. A system comprising:

a journal to store a key value pair to be written to a storage device;

a cache to store the key value pair read from the storage device; and

journal-aware cache logic to evict the key value pair from the cache when the key value pair is written to the journal and to insert the key value pair in the cache when the key value pair is evicted from the journal such that the key value pair is stored in one of the cache or the journal to ensure the key value pair is not duplicated in the journal and the cache, the journal-aware cache logic comprises a least recently used list, each entry in the least recently used list has a pointer to a cache entry in the cache or to a write-ahead-log entry in the journal; and

a display communicatively coupled to a processor to display the key value pair stored in the cache.

7. The system of claim 6 , wherein the key value pair stored in the journal to be written to the storage device in first-in-first-out order.

8. The system of claim 6 , wherein the journal is a non-volatile memory and the cache is a volatile memory.

9. The system of claim 8 , wherein the non-volatile memory is a byte addressable write-in-place memory.

10. A method comprising:

storing a key value pair to be written to a storage device in a journal;

storing the key value pair read from the storage device in a cache; and

evicting, by journal-aware cache logic, the key value pair from the cache when the key value pair is written to the journal; and

inserting, by the journal-aware cache logic, the key value pair in the cache when the key value pair is evicted from the journal such that the key value pair is stored in one of the cache or the journal to ensure the key value pair is not duplicated in the journal and the cache, the journal-aware cache logic comprises a least recently used list, each entry in the least recently used list has a pointer to a cache entry in the cache or to a write-ahead-log entry in the journal.

11. The method of claim 10 , wherein data stored in the journal to be written to the storage device in first-in-first-out order.

12. The method of claim 10 , wherein the journal is a pseudo non-volatile memory in the storage device.

13. The method of claim 10 , wherein the journal is a non-volatile memory and the cache is a volatile memory.

14. The method of claim 13 , wherein the non-volatile memory is a byte addressable write-in-place memory.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2023
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP.
Reel/Frame 062702/0048 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2019
From: RAY, MADHURIMA; TRIKA, SANJEEV N.
To: INTEL CORPORATION
Reel/Frame 047890/0517 →
Continuity (1)
Related Publication 20190108137A1 · Apr 11, 2019