Memory latency management
Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.
1. A remote memory apparatus comprising:
a nonvolatile memory; and
a remote memory controller comprising logic to:
receive a data request from a requestor via a data bus for data stored in the nonvolatile memory;
retrieve the data from the nonvolatile memory;
determine whether the data bus is in an idle state; and
in response to a determination that the data bus is in an idle state, the logic is further configured to:
begin sending the data from the remote memory controller to the requestor over the data bus while the data is being retrieved from the nonvolatile memory to the remote memory controller;
initiate an error correction code algorithm on the data while the data is being sent to the requestor; and
send an error correction code indicator to the requestor over the data bus; or
in response to a determination that the data bus is not in an idle state, the logic is further configured to:
initiate an error correction code algorithm on the data;
correct any errors in the data; and
subsequently send the data to the requestor.
2. The apparatus of claim 1 , wherein, in response to the determination that the data bus is in an idle state, the logic is further configured to:
estimate a delay time needed to execute the error correction code algorithm; and
delay the beginning of sending the data from the remote memory controller to the requestor by the delay time.
3. The apparatus of claim 2 , wherein, in response to the error correction code indicator indicating that the data contains at least one error, the logic is further configured to:
send, to the requestor, a retry error correction code indicator;
correct the at least one error; and
send the corrected data over the data bus to the requestor.
4. The apparatus of claim 3 , wherein the nonvolatile memory comprises three dimensional (3D) cross point memory.
5. A memory controller comprising logic to:
receive a request from a requestor via a data bus for data stored in a nonvolatile memory;
retrieve the data from the nonvolatile memory;
determine whether the data bus is in an idle state; and
in response to a determination that the data bus is in an idle state, the logic is further configured to;
begin transmission of the data from the memory controller to the requestor over the data bus;
initiate an error correction code algorithm after the data has begun transmission; and
transmit an error correction code indicator to the requestor over the data bus; or
in response to a determination that the data bus is not in an idle state, the logic is further configured to:
initiate an error correction code algorithm on the data;
correct any errors in the data; and
subsequently send the data to the requestor.
6. The memory controller of claim 5 , wherein, in response to the determination that the data bus is in an idle state, the logic is further configured to:
estimate a delay time needed to execute the error correction control algorithm; and
delay beginning transmission of the data to the requestor by the delay time.
7. The memory controller of claim 5 , wherein, in response to the error correction code indicator indicating that the data contains at least one error, the logic is further configured to:
transmit, to the requestor, a retry error correction code indicator;
correct the at least one error; and
send the corrected data over the data bus to the requestor.
8. The memory controller of claim 7 , wherein the nonvolatile memory comprises three dimensional (3D) cross point memory.