Erase management in memory systems
Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system.
1. A method comprising:
in response to receiving a notification that data stored in a region of storage cells in a non-volatile memory system is invalid data, marking the region as storing the invalid data;
limiting an amount of time that the region of storage cells is in an erase state associated with subsequent overwriting of the invalid data in the storage cells with replacement data; and
wherein limiting the amount of time includes: delaying an operation of erasing the invalid data in the storage cells in the region, the delayed operation reducing the time to below a predetermined time threshold value.
2. The method as in claim 1 , wherein limiting the amount of time further includes:
subsequent to erasing the invalid data in the storage cells in the region, storing the replacement data in the erased storage cells.
3. The method as in claim 1 , wherein delaying the operation of erasing the invalid data includes:
monitoring a need for storage space in the non-volatile memory system; and
erasing the invalid data in the storage region in response to detecting a need to store the replacement data in the non-volatile memory system.
4. The method as in claim 3 further comprising:
subsequent to erasing the invalid data, initiating storage of the replacement data in the storage cells of the region to ensure that the amount of time in which the storage cells are set to an erased state is below the predetermined time threshold value.
5. The method as in claim 1 , wherein limiting the amount of time includes:
reducing a rate of intrinsic charge loss associated with the replacement data stored in the storage cells, the rate of intrinsic charge loss depending on the time in which the settings of the storage cells are set to the erase state prior to storage of the replacement data in the storage cells.
6. The method as in claim 1 , wherein limiting the amount of time includes:
maintaining the settings of the storage cells in a previously programmed state of storing the invalid data until receiving a command to erase the storage cells, the command received in response to detecting that a reserve band in the non-volatile memory system has been reallocated as a current band in which to store newly received data; and
designating the erased region of storage cells as being the reserve band.
7. The method as in claim 1 further comprising:
receiving a command to modify the invalid data in the storage cells; and
in response to receiving the command, modifying a less-than-all portion of the settings of the storage cells in the region to be in a non-erase state in which the invalid data becomes corrupted.
8. The method as in claim 7 , wherein modifying the less-than-all portion of settings of the storage cells to the non-erase state includes:
changing settings of a first group of cells in the region from a first non-erase state to a second non-erase state to render the invalid data unavailable.
9. The method as in claim 1 further comprising:
increasing an erase threshold voltage value associated with the storage cells; and
modifying settings of the storage cells to fall within a range defined by the increased erase threshold voltage value.
10. The method as in claim 1 further comprising:
performing a partial erase of the region to delete the invalid data.
11. The method as in claim 1 , wherein limiting the amount of time includes:
erasing the region of storage cells to delete the invalid data; and
programming the region of storage cells with temporary data prior to overwriting of the temporary data with the replacement data.
12. The method as in claim 1
wherein limiting the amount of time includes: reducing a rate of intrinsic charge loss associated with the replacement data stored in the storage cells.
13. The method as in claim 1 , wherein limiting the amount of time includes: controlling the amount of time to be below a threshold value.
14. The method as in claim 1 , wherein marking the region includes:
modifying data stored at a predetermined location in the region to indicate that the region includes invalid data, the method further comprising:
utilizing settings of the data at the predetermined location to determine that the region stores invalid data.
15. The method as in claim 1 , wherein limiting the amount of time includes: activating a timer to track the amount of time that the region of storage cells is in the erase state.
16. The method as in claim 15 further comprising:
in response to detecting that the timer reaches a time threshold value indicating that the region of storage cells has been in the erase state for a pre-determined amount of time, completing writing of data to any unwritten portion of the region of storage cells.
17. The method as in claim 16 further comprising:
subsequent to erasing the invalid data in the region of storage cells, writing new data to the storage cells in the region on an as-needed basis as the new data becomes available for storage.
18. The method as in claim 1 further comprising:
subsequent to erasing the invalid data in the region of storage cells, writing new data to the storage cells in the region on an as-needed basis as the new data becomes available for storage.
19. An apparatus for storing data, the apparatus comprising:
a non-volatile memory system including multiple non-volatile memory devices; and
processing logic configured to:
receive notification that data stored in a region of storage cells in the non-volatile memory system is invalid data;
in response to the notification, mark the region as storing the invalid data; and
limit an amount of time that the region is set to an erase state associated with subsequent overwriting of the invalid data in the storage cells with replacement data, the amount of time limited to below a threshold value.
20. The apparatus as in claim 19 ,
wherein the processing logic is further configured to delay an operation of erasing the invalid data in the storage cells in the region and replacing the invalid data with the replacement data, the delayed operation reducing the time to below the threshold value.
21. The apparatus as in claim 20 , wherein the processing logic is further configured to:
monitor a need for storage space in the non-volatile memory system; and
erase the invalid data in the storage region in response to detecting a need to store the replacement data in the non-volatile memory system.
22. The apparatus as in claim 21 , wherein the processing logic is further configured to:
subsequent to erasing the invalid data, initiate storage of the replacement data in the storage cells of the region to ensure that the time in which the storage cells are set to the erased state is below the threshold value.
23. The apparatus as in claim 20 , wherein the processing logic is further configured to:
reduce a rate of intrinsic charge loss associated with the replacement data stored in the storage cells, the rate of intrinsic charge loss depending on an amount of the time in which the settings of the storage cells are set to the erase state prior to storage of the replacement data in the storage cells.
24. The apparatus as in claim 19 , wherein the processing logic is further configured to:
maintain the settings of the storage cells in a previously programmed state of storing the invalid data until receiving a command to erase the storage cells, the command received in response to detecting that a reserve band in the non-volatile memory system has been reallocated as a current band in which to store newly received data.
25. A computer system including the apparatus in claim 19 , the computer system further comprising:
host computer processor hardware configured to communicate with the processing logic and store the corresponding data in the memory system.
26. A computer system including the apparatus in claim 19 , wherein the non-volatile memory system is a solid-state drive to which the computer system has access.
27. The computer system as in claim 26 , the computer system further comprising:
a display screen on which to render an image based at least in part on the corresponding data stored in the solid state-drive.
28. Non-transitory computer-readable media having instructions stored thereon, the instructions, when carried out by computer processor hardware, cause the computer processor hardware to perform operations of:
in response to receiving a notification that a region of storage cells in a non-volatile memory system stores invalid data, marking the region as storing the invalid data;
limiting a time that the region of storage cells is in an erase state before subsequent overwriting of the storage cells with replacement data; and
wherein limiting the time includes: controlling the time to be below a threshold value.
29. The non-transitory computer-readable media as in claim 28 , wherein controlling the time includes: delaying an operation of erasing the invalid data in the storage cells in the region and replacing the invalid data with the replacement data, the delayed operation reducing the time to below the threshold value.