Flexible wear management for non-volatile memory
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.
1. A method of performing memory cell wear management in a computer system that employs a near memory and a far memory, comprising:
keeping track of a first number of write cycles that a first memory portion of the far memory has been subjected to, the first memory portion having a first physical memory address;
in response to the first number of write cycles for the first memory portion having exceeded a first specified threshold, swapping the first physical memory address with a second physical memory address, the second physical memory address corresponding to a second memory portion of the far memory that has been subjected to a second number of write cycles below the first specified threshold;
performing a data write operation on the second memory portion having the second physical memory address; and
in response to a predetermined event, incrementing the first specified threshold by a predetermined amount.
2. The method of claim 1 further comprising:
randomly generating the second physical memory address.
3. The method of claim 2 wherein the randomly generating of the second physical memory address includes randomly generating one or more physical memory addresses until the second physical memory address corresponding to the second memory portion that has been subjected to the number of write cycles below the first specified threshold is generated.
4. The method of claim 3 wherein the predetermined event corresponds to randomly generating more than a specified number of physical memory addresses, and wherein the incrementing of the first specified threshold includes incrementing the first specified threshold by the predetermined amount in the event more than the specified number of physical memory addresses have been randomly generated.
5. The method of claim 1 further comprising:
determining that the second memory portion having the second physical memory address has been subjected to a third number of write cycles that exceeds the first specified threshold; and
unswapping the first physical memory address and the second physical memory address.
6. The method of claim 1 further comprising:
determining that the second physical memory address has been previously swapped with another physical memory address; and
unswapping the second physical memory address and the other physical memory address prior to the swapping of the first physical memory address with the second physical memory address.
7. The method of claim 1 further comprising:
determining that the first memory portion having the first physical memory address has been subjected to a third number of write cycles that exceeds a second specified threshold.
8. The method of claim 7 further comprising:
determining that the second memory portion has been subjected to the second number of write cycles that is below one or both of the first specified threshold and the second specified threshold.
9. The method of claim 8 wherein the incrementing of the first specified threshold by the predetermined amount includes incrementing one or both of the first specified threshold and the second specified threshold by the predetermined amount.
10. The method of claim 1 wherein the near memory comprises a volatile memory, and the far memory comprises a non-volatile memory.
11. The method of claim 1 wherein the near memory comprises a dynamic random access memory (DRAM), and the far memory comprises one or more of (1) NAND or NOR flash memory that uses a single bit per memory cell, (2) multi-level cell (MLC) memory, (3) NAND flash memory with two bits per cell, (4) polymer memory, (5) phase-change memory (PCM), (6) stacked PCM cell arrays that use phase-change memory and switch (PCMS) technology, (7) nanowire-based charge-trapping memory, (8) ferroelectric transistor random access memory (FeTRAM), and (9) 3-dimensional cross-point memory.
12. An apparatus for performing memory cell wear management, comprising:
a near memory and a far memory, the far memory including at least a first memory portion having a first physical memory address, and a second memory portion having a second physical memory address; and
at least one controller operative:
to keep track of a first number of write cycles that the first memory portion has been subjected to;
in response to the first number of write cycles for the first memory portion having exceeded a first specified threshold, to swap the first physical memory address with the second physical memory address prior to performing a data write operation on the second memory portion, the second memory portion having been subjected to a second number of write cycles below the first specified threshold; and
in response to a predetermined event, to increment the specified threshold by a predetermined amount.
13. The apparatus of claim 12 wherein the at least one controller is further operative to randomly generate the second physical memory address.
14. The apparatus of claim 13 wherein the at least one controller is further operative to randomly generate one or more physical memory addresses until the second physical memory address corresponding to the second memory portion that has been subjected to the number of write cycles below the specified threshold is generated.
15. The apparatus of claim 14 wherein the predetermined event corresponds to randomly generating more than a specified number of physical memory addresses, and wherein the at least one controller is further operative to increment the specified threshold by the predetermined amount in the event more than the specified number of physical memory addresses have been randomly generated.
16. The apparatus of claim 12 wherein the at least one controller is further operative:
to determine that the second memory portion having the second physical memory address has been subjected to a third number of write cycles that exceeds the specified threshold; and
to unswap the first physical memory address and the second physical memory address.
17. The apparatus of claim 12 further comprising:
a processor communicatively coupled to the at least one controller.
18. The apparatus of claim 12 wherein the near memory comprises a volatile memory, and the far memory comprises a non-volatile memory.
19. The apparatus of claim 12 wherein the near memory comprises a dynamic random access memory (DRAM), and the far memory comprises one or more of (1) NAND or NOR flash memory that uses a single bit per memory cell, (2) multi-level cell (MLC) memory, (3) NAND flash memory with two bits per cell, (4) polymer memory, (5) phase-change memory (PCM), (6) stacked PCM cell arrays that use phase-change memory and switch (PCMS) technology, (7) nanowire-based charge-trapping memory, (8) ferroelectric transistor random access memory (FeTRAM), and (9) 3-dimensional cross-point memory.
20. A method of performing memory cell wear management in a computer system that employs a near memory and a far memory, comprising:
keeping track of one or both of a first number of write cycles and a first number of read cycles that a first memory portion of the far memory has been subjected to, the first memory portion having a first physical memory address;
in response to one or both of the first number of write cycles and the first number of read cycles for the first memory portion having exceeded a first specified threshold, swapping the first physical memory address with a second physical memory address, the second physical memory address corresponding to a second memory portion of the far memory that has been subjected to one or both of a second number of write cycles and a second number of read cycles below the first specified threshold;
performing a data write operation on the second memory portion having the second physical memory address; and
in response to a predetermined event, incrementing the specified threshold by a predetermined amount.
21. The method of claim 20 further comprising:
randomly generating the second physical memory address.
22. The method of claim 21 wherein the randomly generating of the second physical memory address includes randomly generating one or more physical memory addresses until the second physical memory address corresponding to the second memory portion that has been subjected to the number of read cycles below the specified threshold is generated.
23. The method of claim 22 wherein the predetermined event corresponds to randomly generating more than a specified number of physical memory addresses, and wherein the incrementing of the specified threshold includes incrementing the specified threshold by the predetermined amount in the event more than the specified number of physical memory addresses have been randomly generated.
24. The method of claim 20 wherein the near memory comprises a volatile memory, and the far memory comprises a non-volatile memory.
25. The method of claim 20 wherein the near memory comprises a dynamic random access memory (DRAM), and the far memory comprises one or more of (1) NAND or NOR flash memory that uses a single bit per memory cell, (2) multi-level cell (MLC) memory, (3) NAND flash memory with two bits per cell, (4) polymer memory, (5) phase-change memory (PCM), (6) stacked PCM cell arrays that use phase-change memory and switch (PCMS) technology, (7) nanowire-based charge-trapping memory, (8) ferroelectric transistor random access memory (FeTRAM), and (9) 3-dimensional cross-point memory.