Non-uniform iteration-dependent min-sum scaling factors for improved performance of spatially-coupled LDPC codes

1. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic is to:

receive a codeword containing a spatially-coupled low-density parity-check (SC-LDPC) code; and

conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors, wherein the scaling factors are to be non-uniform across multiple iterations of the min-sum decode so that the plurality of scaling factors are adjusted in response to a determination that a maximum number of iterations has not been reached, and wherein variation of the scaling factors to be non-uniform across the multiple iterations is performed while also keeping the scaling factors non-uniform across a plurality of check nodes so as to maintain a synchronization with a wave-shape associated with the SC-LDPC code across the multiple iterations.

2. The semiconductor apparatus of claim 1 , wherein the scaling factors are to cause a wave propagation of the min-sum decode.

3. The semiconductor apparatus of claim 2 , wherein the min-sum decode is to decode variable nodes at a boundary of the SC-LDPC.

4. The semiconductor apparatus of claim 1 , wherein the logic coupled to the one or more substrates is to select the scaling factors based on a performance of the min-sum decode.

5. The semiconductor apparatus of claim 4 , wherein the logic coupled to the one or more substrates is to conduct a density evolution analysis to determine the performance of the min-sum decode.

6. The semiconductor apparatus of claim 1 , wherein the codeword is to be received from a NAND memory structure.

7. A system comprising:

a memory structure; and

a memory controller coupled to the memory structure, wherein the memory controller includes logic coupled to one or more substrates to:

receive a codeword containing a spatially-coupled low-density parity-check (SC-LDPC) code, wherein the codeword is received from the memory structure; and

conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors, wherein the scaling factors are to be non-uniform across multiple iterations of the min-sum decode so that the plurality of scaling factors are adjusted in response to a determination that a maximum number of iterations has not been reached, and wherein variation of the scaling factors to be non-uniform across the multiple iterations is performed while also keeping the scaling factors non-uniform across a plurality of check nodes so as to maintain a synchronization with a wave-shape associated with the SC-LDPC code across the multiple iterations.

8. The system of claim 7 , wherein the scaling factors are to cause a wave propagation of the min-sum decode.

9. The system of claim 8 , wherein the min-sum decode is to decode variable nodes at a boundary of the SC-LDPC.

10. The system of claim 7 , wherein the logic coupled to the one or more substrates is to select the scaling factors based on a performance of the min-sum decode.

11. The system of claim 10 , wherein the logic coupled to the one or more substrates is to conduct a density evolution analysis to determine the performance of the min-sum decode.

12. The system of claim 7 , wherein the memory structure is a NAND memory structure.

13. A method comprising:

receiving a codeword containing a spatially-coupled low-density parity-check (SC-LDPC) code; and

conducting a min-sum decode of the SC-LDPC code based on a plurality of scaling factors, wherein the scaling factors are to be non-uniform across multiple iterations of the min-sum decode so that the plurality of scaling factors are adjusted in response to a determination that a maximum number of iterations has not been reached, and wherein varying the scaling factors to be non-uniform across the multiple iterations is performed while also keeping the scaling factors non-uniform across a plurality of check nodes so as to maintain a synchronization with a wave-shape associated with the SC-LDPC code across the multiple iterations.

14. The method of claim 13 , wherein the scaling factors cause a wave propagation of the min-sum decode.

15. The method of claim 14 , wherein the min-sum decode decodes variable nodes at a boundary of the SC-LDPC.

16. The method of claim 13 , further including selecting the scaling factors based on a performance of the min-sum decode.

17. The method of claim 16 , further including conducting a density evolution analysis to determine the performance of the min-sum decode.