Apparatus, system, and method for decoding linear block codes in a memory controller

1. An apparatus comprising:

a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion;

an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword;

a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder;

a queue, coupled to the second logic unit, to store the first parity portion concatenated with a compressed zero data bit; and

a correction unit to correct the data portion of the codeword via the generated first parity portion.

2. The apparatus of claim 1 further comprises:

a decoder to receive the first parity portion and to determine error locations in the data portion of the received codeword via the first parity portion,

wherein the queue is coupled to the decoder.

3. The apparatus of claim 2 , wherein the encoder is configured to encode a linear block code which is systematic, and wherein the second logic unit is configured to generate the first parity portion by applying a logical exclusive-OR operation to the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder.

4. The apparatus of claim 2 , wherein the encoder is a BCH encoder and the decoder is a BCH decoder, the BCH decoder comprises:

a single syndrome calculation unit to generate a syndrome from the first parity portion;

a third logic unit operable to execute a Berlekamp-Massey algorithm on the syndrome; and

a fourth logic unit operable to execute a Chien Search algorithm on the output of the third logic unit.

5. The apparatus of claim 2 , wherein the encoder is a Low-Density Parity-Check Code (LDPC) encoder and the decoder is a LDPC decoder.

6. The apparatus of claim 2 , wherein the correction unit is operable to receive the determined error locations from the decoder and the data portion of the received codeword to generate the corrected data.

7. The apparatus of claim 1 , wherein the encoder is configured to encode a linear block code which is systematic, wherein the encoder comprises a Cyclic Redundancy Check (CRC) encoder and a Low-Density Parity-Check Code (LDPC) encoder, and wherein the first parity portion comprises LDPC parity bits and CRC parity bits.

8. A system comprising:

a memory;

a controller coupled to the memory, the controller comprising:

a first logic unit to receive codeword from the memory, the codeword having a data portion and a corresponding parity portion;

an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword;

a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder;

a queue, coupled to the second logic unit, to store the first parity portion concatenated with a compressed zero data bit; and

a correction unit to correct the data portion of the codeword via the generated first parity portion; and

a processor coupled to the controller to receive the corrected data portion.

9. The system of claim 8 , wherein the memory is a NAND flash memory, and wherein the controller is a Solid State Drive (SSD) controller.

10. The system of claim 8 further comprises:

a decoder to receive the first parity portion and to determine error locations in the data portion of the codeword via the first parity portion,

wherein the queue is coupled to the decoder.

11. The system of claim 10 , wherein the encoder is configured to encode a linear block code which is systematic, and wherein the second logic unit is configured to generate the first parity portion by applying a logical exclusive-OR operation to the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder.

12. The system of claim 10 , wherein the encoder is a BCH encoder and the decoder is a BCH decoder, the BCH decoder comprises:

a single syndrome calculation unit to generate a syndrome from the first parity portion;

a third logic unit operable to execute a Berlekamp-Massey algorithm on the syndrome; and

a fourth logic unit operable to execute a Chien Search algorithm on the output of the third logic unit.

13. The system of claim 10 , wherein the encoder is a Low-Density Parity-Check Code (LDPC) encoder and the decoder is a LDPC decoder.

14. The system of claim 10 , wherein the correction unit is operable to receive the determined error locations from the decoder and the data portion of the received codeword to generate the corrected data.

15. The system of claim 8 , wherein the encoder is configured to encode a linear block code which is systematic, wherein the encoder comprises a Cyclic Redundancy Check (CRC) encoder and a Low-Density Parity-Check Code (LDPC) encoder, and wherein the first parity portion comprises LDPC parity bits and CRC parity bits.

16. A method comprising:

receiving a codeword from a memory, the codeword having a data portion and a corresponding parity portion, wherein the codeword is a systematic codeword;

encoding the data portion of the received codeword to generate a corresponding parity of the data portion of the received codeword;

generating a first parity portion from the corresponding parity portion of the received codeword and the encoded corresponding parity portion;

queuing the first parity portion which is concatenated with a compressed zero data bit; and

correcting the data portion of the codeword via the generated first parity portion.

17. The method of claim 16 further comprises:

computing, by a decoder, an error location from the first parity portion, the error location in the data portion of the codeword.

18. The method of claim 16 , wherein generating the first parity portion comprises applying a logical exclusive-OR operation to the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder, and

wherein correcting the data portion of the codeword via the generated first parity portion comprises changing bit values at bit locations of the data portion of the received codeword, the bit location corresponding to the determined error locations.

19. A system comprising:

a handheld device; and

a controller communicatively coupled to the handheld device by means of transmission medium, the controller comprising:

a first logic unit to receive codeword from the handheld device, the codeword having a data portion and a corresponding parity portion;

an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword;

a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder;

a queue, coupled to the second logic unit, to store the first parity portion concatenated with a compressed zero data bit; and

a correction unit to correct the data portion of the codeword via the generated first parity portion.

20. The system of claim 19 , wherein the handheld device comprises a NAND flash memory, and wherein the controller is a Solid State Drive (SSD) controller.

21. The system of claim 19 , wherein the handheld device is a smart phone device or a personal computing tablet device.

22. The system of claim 19 further comprises:

a decoder to receive the first parity portion and to determine error locations in the data portion of the codeword via the first parity portion,

wherein the queue is coupled to the decoder.

23. The system of claim 19 , wherein the encoder is configured to encode a linear block code which is systematic, and wherein the second logic unit is configured to generate the first parity portion by applying a logical exclusive-OR operation to the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder.

24. The system of claim 19 , wherein the encoder is configured to encode a linear block code which is systematic, wherein the encoder comprises a Cyclic Redundancy Check (CRC) encoder and a Low-Density Parity-Check Code (LDPC) encoder, and wherein the first parity portion comprises LDPC parity bits and CRC parity bits.