Method to improve mixed workload performance on storage devices that use cached operations
An apparatus for controlling a solid state drive (SSD) includes an host interface, to receive a set of memory access commands from a host computer, and processing circuitry coupled to the host interface and to memory cells of the SSD, to distinguish the write commands from the read commands in the set, and execute up to a threshold number of the write commands prior to executing any of the read commands.
1. An apparatus for controlling a solid state drive (SSD), comprising:
a host interface, to receive a set of memory access commands from a host computer;
processing circuitry including at least one electrically conductive element coupled to the host interface and to memory cells of the SSD, to:
distinguish write commands in the set from read commands in the set;
store the write commands in a write buffer, and store the read commands in a read buffer;
execute up to a first threshold number of the write commands prior to executing any of the read commands; and
move a second threshold number of read commands stored in the read buffer from the read buffer to the write buffer, wherein both the read commands and the write commands are to follow a path for execution out of the write buffer and the processing circuitry is further to execute all of the read commands that were moved to the write buffer prior to storing any new write commands in the write buffer.
2. The apparatus of claim 1 , further comprising the write buffer and the read buffer.
3. The apparatus of claim 1 , wherein the second threshold is greater than the first threshold.
4. The apparatus of claim 1 , wherein the ratio of the second threshold to the first threshold is a rational number between 4 and 6.
5. The apparatus of claim 1 , wherein the set of memory access commands includes both write commands and read commands.
6. The apparatus of claim 1 , wherein the processing circuitry is further to determine if no write commands are included in the set, and in response to the determination, execute up to the second threshold number of the read commands in the set.
7. One or more non-transitory computer-readable storage media comprising a set of instructions, which, when executed by a solid state drive (SSD) controller coupled to memory cells of a SSD, cause the SSD controller to:
receive a set of read and write commands from a host computer;
distinguish between write commands in the set and read commands in the set;
store the write commands in a write buffer of the SSD, and the read commands in a read buffer of the SSD;
execute up to a first threshold number of the write commands prior to executing any of the read commands;
move a second threshold number of read commands stored in the read buffer from the read buffer to the write buffer, wherein both the read commands and the write commands are to follow a path for execution out of the write buffer; and
execute all of the read commands that were moved to the write buffer prior to storing any new write commands in the write buffer.
8. The one or more non-transitory computer-readable storage media of claim 7 , wherein the second threshold number is larger than the first threshold number.
9. The one or more non-transitory computer-readable storage media of claim 7 , wherein the set of memory access commands includes both write commands and read commands.
10. The one or more non-transitory computer-readable storage media of claim 7 , wherein the ratio of the second threshold number to the first threshold number is a rational number between 4 and 6.
11. The one or more non-transitory computer-readable storage media of claim 7 , further comprising instructions, that when executed, cause the SSD controller to: determine if no write commands have been received from the host computer, and in response to the determination, execute up to a second threshold number of the read commands in the set.
12. A memory device, comprising:
a NAND die including at least one memory cell; and
a solid state drive (SSD) controller, comprising:
a host interface, to receive a set of memory access commands from a host computer; and
processing circuitry coupled to the host interface and to the at least one memory cell, to
distinguish write commands in the set from read commands in the set;
store the write commands in a write buffer, and store the read commands in a read buffer; and
execute up to a first threshold number of the write commands prior to executing any of the read commands;
move a second threshold number of read commands stored in the read buffer from the read buffer to the write buffer, wherein both the read commands and the write commands are to follow a path for execution out of the write buffer; and
execute all of the read commands that were moved to the write buffer prior to storing any new write commands from the host computer in the write buffer.
13. The memory device of claim 12 , the SSD controller further comprising the write buffer and the read buffer.
14. The memory device of claim 12 , wherein the processing circuitry of the SSD controller is further to:
continue to store new read commands from the host computer in the read buffer.
15. The memory device of claim 12 , wherein the ratio of the second threshold to the first threshold is a rational number between 4 and 6.