Adaptive configuration of non-volatile memory
Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
1. An apparatus comprising:
a non-volatile memory; and
a mode register to maintain information to indicate default configurations for the non-volatile memory, the default configurations to include:
a default external clock operating frequency,
a default input/output bus width, and
a default command address cycle count;
wherein the mode register is accessible to a controller in order to update the default configurations based on one or more capabilities of the non-volatile memory discoverable by the controller during initialization of the non-volatile memory, the one or more capabilities to include:
available external clock operating frequencies,
available input/output pins,
available command/address pins, and
a mode of operation for the non-volatile memory to include a storage mode or a memory mode;
wherein values included in the mode register following an update to the default configuration indicate:
a selected external clock operating frequency from among the available external clock operating frequencies,
updated input/output bus width based on active input/output pins from among the available input/output pins, and
updated command address cycle count based on active command/address pins from among the available command/address pins.
2. The apparatus of claim 1 , the one or more capabilities further comprising multiple power states to operate the non-volatile memory on a computer platform and indicators to cause the non-volatile memory to transition between power states of the multiple power states.
3. The apparatus of claim 2 , the multiple power states comprise an active power state, an idle power state, a fast standby power state or a slow standby power state.
4. The apparatus of claim 3 , comprising the fast standby power state and the slow standby power state to include the non-volatile memory in a refresh state that includes periodically turning on power consuming circuits to refresh internal paths, the fast standby power state to result in periodically turning on high power consuming circuits at a first rate that is more frequent than a second rate for the slow standby power state.
5. The apparatus of claim 3 , the indicators to cause the non-volatile memory to transition between power states of the multiple power states includes a clock enable indicator to be used to transition the non-volatile memory between at least some of the power states.
6. The apparatus of claim 1 , the active input/output pins and the active command/address pins are based on the mode of operation discoverable by the controller.
7. The apparatus of claim 6 , comprising a higher number of active input/output pins and command/address pins for the memory mode as compared to the number of active input/output pins and command/address pins for the storage mode.
8. The apparatus of claim 1 , comprising the non-volatile memory including phase change memory (PCM).
9. A method comprising:
storing default values to a mode register for a non-volatile memory to indicate default configurations for the non-volatile memory, the default configurations including a default external clock operating frequency, an input/output bus width and a default command address cycle count;
receiving updated values based on one or more capabilities of the non-volatile memory discoverable by a controller during initialization of the non-volatile memory, the one or more capabilities to include available external clock operating frequencies, available input/output pins, available command/address pins and a mode of operation for the non-volatile memory to include a storage mode or a memory mode, the one or more capabilities to include available external clock operating frequencies, available input/output pins, available command/address pins and a mode of operation for the non-volatile memory to include a storage mode or a memory mode; and
storing the updated values in the mode register to enable an available external clock operating frequency, the input/output bus width and an updated command address cycle count to be configured based on the updated values, wherein the updated values indicate a selected external clock operating frequency from among the available external clock operating frequencies, updated input/output bus widths based on active input/output pins from among the available input/output pins and the updated command address cycle count based on active command/address pins from among the available command/address pins.
10. The method of claim 9 , the one or more capabilities further comprising multiple power states to operate the non-volatile memory on a computer platform and indicators to cause the non-volatile memory to transition between power states of the multiple power states.
11. The method of claim 10 , the multiple power states comprise an active power state, an idle power state, a fast standby power state or a slow standby power state.
12. The method of claim 11 , comprising the fast standby power state and the slow standby power state to include the non-volatile memory in a refresh state that includes periodically turning on power consuming circuits to refresh internal paths, the fast standby power state to result in periodically turning on high power consuming circuits at a first rate that is more frequent than a second rate for the slow standby power state.
13. The method of claim 11 , the indicators to cause the non-volatile memory to transition between power states of the multiple power states includes a clock enable indicator to be used to transition the non-volatile memory between at least some of the power states.
14. The method of claim 9 , comprising the non-volatile memory including phase change memory (PCM).
15. The method of claim 9 , comprising the active input/output pins and the active command/address pins are based on the mode of operation discoverable by the controller.
16. The method of claim 15 , comprising a higher number of active input/output pins and command/address pins for the memory mode as compared to the number of active input/output pins and command/address pins for the storage mode.
17. A system comprising:
a controller;
a non-volatile memory; and
a mode register to maintain information to indicate default configurations for the non-volatile memory, the default configuration to include:
a default external clock operating frequency,
a default input/output bus width, and
a default command address cycle count;
wherein the mode register is accessible to the controller in order to update the default configurations based on one or more capabilities of the non-volatile memory discoverable by the controller during initialization of the non-volatile memory, the one or more capabilities to include:
available external clock operating frequencies,
available input/output pins,
available command/address pins, and
a mode of operation for the non-volatile memory to include a storage mode or a memory mode;
wherein values included in the mode register following an update to the default configuration indicate:
a selected external clock operating frequency from among the available external clock operating frequencies,
updated input/output bus width based on active input/output pins from among the available input/output pins, and
updated command address cycle count based on active command/address pins from among the available command/address pins.
18. The system of claim 17 , the one or more capabilities further comprising multiple power states to operate the non-volatile memory on a computer platform and indicators to cause the non-volatile memory to transition between power states of the multiple power states.
19. The system of claim 18 , the multiple power states comprise an active power state, an idle power state, a fast standby power state or a slow standby power state.
20. The system of claim 19 , comprising the fast standby power state and the slow standby power state to include the non-volatile memory in a refresh state that includes periodically turning on power consuming circuits to refresh internal paths, the fast standby power state to result in periodically turning on high power consuming circuits at a first rate that is more frequent than a second rate for the slow standby power state.
21. The system of claim 19 , the indicators to cause the non-volatile memory to transition between power states of the multiple power states includes a clock enable indicator to be used to transition the non-volatile memory between at least some of the power states.
22. The system of claim 17 , the active input/output pins and the active command/address pins are based on the mode of operation discoverable by the controller.
23. The system of claim 22 , comprising a higher number of active input/output pins and command/address pins for the memory mode of operation as compared to the number of active input/output pins and command/address pins for the storage mode of operation.
24. The system of claim 17 , comprising the non-volatile memory including phase change memory (PCM).
25. A controller comprising;
a configuration control logic to:
receive information from a mode register maintained at a non-volatile memory that indicates default configurations for the non-volatile memory, the default configurations to include:
a default external clock operating frequency,
a default input/output bus width, and
a default command address cycle count;
and
update the default configurations based on one or more capabilities of the non-volatile memory discoverable during initialization of the non-volatile memory, the one or more capabilities to include:
available external clock operating frequencies,
available input/output pins,
available command/address pins, and
a mode of operation for the non-volatile memory to include a storage mode or a memory mode;
wherein values included in the mode register following an update to the default configuration indicate:
a selected external clock operating frequency from among the available external clock operating frequencies,
updated input/output bus width based on active input/output pins from among the available input/output pins, and
updated command address cycle count based on active command/address pins from among the available command/address pins.
26. The controller of claim 25 , further comprising:
a power control logic;
the one or more capabilities to also include multiple power states to operate the non-volatile memory on a computer platform; and
the power control logic to use a clock enable indicator to cause the non-volatile memory to transition between at least some of the power states of the multiple power states.
27. The controller of claim 26 , the multiple power states comprise an active power state, an idle power state, a fast standby power state or a slow standby power state.
28. The controller of claim 27 , comprising the fast standby power state and the slow standby power state to include the non-volatile memory in a refresh state that includes periodically turning on power consuming circuits to refresh internal paths, the fast standby power state to result in periodically turning on high power consuming circuits at a first rate that is more frequent than a second rate for the slow standby power state.
29. The controller of claim 25 , the active input/output pins and the active command/address pins are based on the mode of operation discoverable by the configuration control logic.
30. The controller of claim 29 , comprising a higher number of active input/output pins and command/address pins for the memory mode as compared to the number of active input/output pins and command/address pins for the storage mode.
31. The controller of claim 25 , comprising the non-volatile memory including phase change memory (PCM).