Low density parity check (LDPC) decoder architecture with check node storage (CNS) or bounded circulant
A low-density parity-check (LDPC) decoder has a check node storage (CNS) architecture to reduce the gate count for the decoder implementation, resulting in a lower footprint relative to traditional designs. The CNS architecture allows a controller to selectively, dynamically swap check nodes of the LDPC decoder between latching circuitry and a volatile memory. The controller can to store active check nodes in the latching circuitry and check nodes not active for a computation in the volatile memory.
1. An apparatus comprising:
a volatile memory array to store inactive check nodes for a low-density parity-check (LDPC) decoder;
latching circuitry to store active check nodes for the LDPC decoder; and
a controller to dynamically move check nodes from the volatile memory array to the latching circuitry that are active for an H-matrix operation of an LDPC code and to dynamically move check nodes from the volatile latching circuitry to the volatile memory array that are inactive for the H-matrix operation of the LDPC code.
2. The apparatus of claim 1 , wherein the volatile memory array comprises a synchronous random access memory (SRAM) array.
3. The apparatus of claim 1 , wherein the latching circuitry comprises multiple groups of latches, where a group of latches is to store an active check node.
4. The apparatus of claim 1 , wherein the latching circuitry comprises multiple groups of flip-flops, where a group of flip-flops is to store an active check node.
5. The apparatus of claim 1 , wherein the active check nodes comprise check nodes having an offset of an identity matrix circulant constrained for the check nodes of the LDPC decoder.
6. The apparatus of claim 5 , wherein the identity matrix circulant is constrained between zero and one-half of a size of the circulant.
7. The apparatus of claim 1 , wherein the LDPC decoder comprises an LDPC decoder of a memory subsystem.
8. The apparatus of claim 7 , wherein the controller comprises a controller of a printed circuit board (PCB) of a memory module having multiple memory dies.
9. The apparatus of claim 1 , wherein the LDPC decoder comprises an LDPC decoder of a communication subsystem.
10. The apparatus of claim 9 , wherein the controller comprises a controller of an optical communication transceiver.
11. A system, comprising:
a receiver to receive a high bandwidth signal; and
a low-density parity-check (LDPC) decoder to apply error correction to the received high bandwidth signal, the decoder including
a synchronous random access memory (SRAM) array to store inactive check nodes for the LDPC decoder;
flip-flops to store active check nodes for the LDPC decoder; and
a controller to dynamically move check nodes from the SRAM array to the flip-flops that are active for an H-matrix operation of an LDPC code and to dynamically move check nodes from the flip-flops to the SRAM that are inactive for the H-matrix operation of the LDPC code.
12. The system of claim 11 , wherein the flip-flops comprise multiple groups of flip-flops, where a group of flip-flops is to store an active check node.
13. The system of claim 11 , wherein the active check nodes comprise check nodes having an offset of an identity matrix circulant constrained for the check nodes of the LDPC decoder.
14. The system of claim 13 , wherein the identity matrix circulant is constrained between zero and one-half of a size of the circulant.
15. The system of claim 11 , wherein receiver is to receive memory data, and wherein the LDPC decoder comprises an LDPC decoder of a memory subsystem.
16. The system of claim 15 , wherein the controller comprises a controller of a printed circuit board (PCB) of a memory module having multiple memory dies.
17. The system of claim 11 , wherein receiver is to receive optical communication, and wherein the LDPC decoder comprises an LDPC decoder of a communication subsystem.
18. The system of claim 17 , wherein the controller comprises a controller of an optical communication transceiver.
19. The system of claim 11 , further comprising one or more of:
a host processor device coupled to the receiver;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.