IP Library Assignment 020646/0712
Patent Assignment
Reel/Frame 020646/0712

Assignment of Assignor's Interest

Recorded: 2008-03-13 Pages: 5
Assignor
BOSE, SUBHASIS
Executed: 2007-09-10
Assignee
LIGHTSPEED LOGIC, INC.
3255 SCOTT BLVD., STE. 2-102, SANTA CLARA, CALIFORNIA, 95054
Covered Properties (4)
Methods and Systems for Placement
Generalized Clock Tree Synthesis
Timing Driven Buffering and Resizing for Structured Array Architectures
Application: 60/747,651 →
Timing Driven Force Directed Placement Flow
Application: 60/803,032 →
Related Assignments (1)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Dec 12, 2008
From: LIGHTSPEED LOGIC, INC.
To: OTRSOTECH, LLC
Reel/Frame 021965/0767 →