IP Library › Assignment 021965/0767
Patent Assignment
Reel/Frame 021965/0767

Assignment of Assignor's Interest

Recorded: 2008-12-12 Received: 2008-12-12 Pages: 17
Assignor
LIGHTSPEED LOGIC, INC.
Executed: 2008-11-01
Assignee
OTRSOTECH, LLC
2711 CENTERVILLE ROAD, SUITE 400, WILMINGTON, DE, 19808, UNITED STATES
Covered Properties (45)
Incremental Relative Slack Timing Force Model
Application: 11/967,179 →
Timing Driven Force Directed Placement Flow
Application: 11/967,180 →
Tunneling as a Boundary Congestion Relief Mechanism
Application: 11/967,185 →
Node Spreading via Artificial Density Enhancement to Reduce Routing Congestion
Application: 11/967,184 →
Mutable Cells for Use in Integrated Circuits
Application: 11/953,048 →
Simultaneous Dynamical Integration Applied to Detailed Placement
Generalized Clock Tree Synthesis
Methods and Systems for Placement
Transparent Test Method and Scan Flip-Flop
Morphing for Global Placement Using Integer Linear Programming
Methods and Systems for Placement
Methods and Systems for Placement
Application: 11/684,522 →
Alterable Cells for use in Integrated Circuits
Application: 60/869,250 →
Increased Effective Flip-Flop Density in a Structured Asic
Application: 11/456,219 →
Methods and Systems for Placement
Methods and Systems for Placement and Routing
Application: 60/805,086 →
Transparent Test Method and Scan Flip-Flop
Application: 60/805,087 →
Simultaneous Dynamical Integration Applied to Detailed Placement
Application: 60/804,826 →
Generalized Clock Tree Synthesis for Structured Array Fabric
Application: 60/804,690 →
Incremental Relative Slack Timing Force Model
Application: 60/804,574 →
Tunneling as a Boundary Congestion Relief Mechanism
Application: 60/804,643 →
Node Spreading via Artificial Density Enhancement as a Means to Reduce Routing Congestion
Application: 60/804,448 →
Transparent Test Method and Scan Flip-Flop
Application: 60/804,283 →
Morphing for Global Placement Using Integer Linear Programming
Application: 60/804,173 →
Timing Driven Force Directed Placement Flow
Application: 60/803,032 →
Timing Driven Buffering and Resizing for Structured Array Architectures
Application: 60/747,651 →
Asic Customization with Predefined via Mask
Application: 11/277,253 →
Increased effective flip-flop density in a structured ASIC
Application: 60/705,937 →
Method and apparatus for increasing flip-flop density in a structured ASIC
Application: 60/697,918 →
Methods and systems for placement and routing
Application: 60/697,902 →
Methods and systems for placement and routing
Application: 60/696,661 →
Methods and systems for placement and routing
Application: 60/694,949 →
Modular Array Defined by Standard Cell Logic
Implementing Programmable Logic Array Embedded in Mask - Programmed Asic
Application: 10/640,171 →
Function Block Architecture for Gate Array and Method for Forming an Asic
Application: 10/460,343 →
Depopulated Programmable Logic Array
Application: 10/458,892 →
Asic Customization with Predefined via Mask
Application: 10/447,466 →
Modular Array Defined by Standard Cell Logic
Application: 10/447,465 →
High Speed Differential Receiver
Application: 10/161,931 →
Method and Apparatus for Built-in Self-Test of Logic Circuits with Multiple Clock Domains
Application: 10/093,767 →
Method and Apparatus for Controlling and Observing Data in a Logic Block-Based Asic
Application: 10/056,686 →
Asic Routing Architecture
Application: 10/051,237 →
Function Block Architecture with Variable Drive Strengths
Application: 10/020,469 →
Programmable Logic Array Embedded in Mask-Programmed Asic
Application: 09/877,170 →
Depopulated Programmable Logic Array
Application: 09/827,015 →