Implementing programmable logic array embedded in mask-programmed ASIC
View Patent ↗In accordance with the invention, a method for customizing a one-time configurable integrated circuit to include a multi-time configurable structure is disclosed. Such a method includes, in one embodiment receiving a description of circuit functionality from a user for implementation in the one-time configurable device, where the functionality includes a portion that is designated by the user to be reconfigurable. A method in accordance with an embodiment of the invention then models a reconfigurable structure that has enough capacity to accommodate the designated functionality. Optionally, some embodiments of the invention add in more capacity than is required to implement the designated functionality to allow for future reprogramming. The method then embeds the reconfigurable structure in the one-time configurable device. In certain embodiments, the one-time configurable device can be a mask-programmed MBA, gate array, or standard cell, while the reconfigurable structure is a PLA or modified PLA.
1. A method for creating a mask-programmed integrated circuit that includes a reprogrammable structure, comprising:
(a) receiving a description of circuit functionality specified by a user for implementation with the mask-programmed integrated circuit, the description of circuit functionality including a description of non-reprogrammable functionality and descriptions of a plurality of different programmable functionalities to be later programmable into the reprogrammable structure of the mask-programmed integrated circuit to implement one of the different programmable functionalities;
(b) automatically modeling the reprogrammable structure to be capable of alternatively implementing each of the programmable functionalities;
(c) performing physical layout for the entire mask-programmed integrated circuit, including the reprogrammable structure as well as circuitry to accommodate the non-reprogrammable functionality,
wherein the physical layout for the reprogrammable structure is customized.
2. The method of claim 1 , wherein step (b) includes automatically modeling the reprogrammable structure to accommodate the largest of the programmable functionalities.
3. The method of claim 1 , wherein step (b) includes automatically modeling the reprogrammable structure to accommodate a union of the programmable functionalities.
4. The method of claim 1 , wherein step (b) includes automatically modeling the reprogrammable structure with added capacity.
5. The method of claim 1 , wherein step (c) includes: (i) performing physical
layout for the reprogrammable structure; and (ii) subsequently, performing physical layout
for the rest of the circuit functionality.
6. The method of claim 1 further including:
(d) fabricating the mask-programmed integrated circuit.
7. The method of claim 6 , further including:
generating a programming pattern for one of the programmable functionalities;
programming the reprogrammable structure within the mask-programmed integrated circuit based on the programming pattern.
8. The method of claim 1 , wherein step (c) includes performing physical layout for the entire mask-programmed integrated circuit using a predefined array.
9. The method of claim 8 , wherein the predefined array includes one of a module based array and a gate array.
10. The method of claim 1 , wherein the reprogrammable structure is functionally equivalent to a PLA.
11. A method for creating a mask-programmed integrated circuit that includes a reprogrammable structure, comprising:
(a) receiving a description of circuit functionality specified by a user for implementation with the mask-programmed integrated circuit, the description of circuit functionality including a description of non-reprogrammable functionality and descriptions of a plurality of different programmable functionalities to be later programmable into the reprogrammable structure of the mask-programmed integrated circuit to implement one of the different programmable functionalities;
(b) automatically modeling a reprogrammable structure to be capable of implementing the largest of the programmable functionalities;
(c) performing physical layout for the entire mask-programmed integrated circuit, including the reprogrammable structure as well as circuitry to accommodate the non-reprogrammable functionality,
wherein the physical layout for the reprogrammable structure is customized.
12. The method of claim 11 , wherein step (b) includes automatically modeling the reprogrammable structure with added capacity.
13. The method of claim 11 , wherein step (c) includes performing physical layout for the entire mask-programmed integrated circuit using a predefined array.
14. The method of claim 13 , wherein the predefined array includes one of a module based array and a gate array.
15. The method of claim 11 , wherein the reprogrammable structure is functionally equivalent to a PLA.
16. A method for creating a mask-programmed integrated circuit that includes a reprogrammable structure, comprising:
(a) receiving a description of circuit functionality specified by a user for implementation with the mask-programmed integrated circuit, the description of circuit functionality including a description of non-reprogrammable functionality and descriptions of a plurality of different programmable functionalities to be later programmable into the reprogrammable structure of the mask-programmed integrated circuit to implement one of the different programmable functionalities;
(b) automatically modeling a reprogrammable structure to be capable of implementing the largest of the programmable functionalities and that includes added capacity;
(c) performing physical layout for the entire mask-programmed integrated circuit, including the reprogrammable structure as well as circuitry to accommodate the non-reprogrammable, wherein the physical layout for the reprogrammable structure is customized;
(d) fabricating the mask-programmed integrated circuit;
(e) generating a programming pattern for one of the programmable functionalities; and
(f) programming the reprogrammable structure within the mask-programmed integrated circuit based on the programming pattern.
17. The method of claim 16 , wherein step (c) includes performing physical layout for the entire mask-programmed integrated circuit using a predefined array.
18. The method of claim 17 , wherein the predefined array includes one of a module based array and a gate array.
19. The method of claim 16 , wherein the reprogrammable structure is functionally equivalent to a PLA.
20. A computer readable medium having a set of instructions stored therein for use in creating a mask-programmed integrated circuit that includes a reprogrammable portion, which when executed by a computer causes the computer to perform the steps of:
(a) receiving a description of circuit functionality specified by a user for implementation with the mask-programmed integrated circuit, the description of circuit functionality including a description of non-reprogrammable functionality and descriptions of a plurality of different programmable functionalities to be later programmable into the reprogrammable structure of the mask-programmed integrated circuit to implement one of the different programmable functionalities;
(b) automatically modeling a reprogrammable structure that is capable of alternatively implementing each of the programmable functionalities;
(c) performing physical layout for the entire mask-programmed integrated circuit, including the reprogrammable structure as well as circuitry to accommodate the non-reprogrammable functionality,
wherein the physical layout for the reprogrammable structure is customized.
21. The computer readable medium of claim 20 , wherein step (b) includes automatically modeling the reprogrammable structure to accommodate the largest of the programmable functionalities.
22. The computer readable medium of claim 20 , wherein step (b) includes automatically modeling the reprogrammable structure to accommodate a union of the programmable functionalities.
23. The computer readable medium of claim 20 , wherein step (b) includes automatically modeling said reprogrammable structure with added capacity.
24. The computer readable medium of claim 20 , wherein step (c) includes: (i) performing physical layout for the reprogrammable structure; and subsequently, performing physical layout for the rest of the circuit functionality.
25. The computer readable medium of claim 20 , further including instructions for performing the step of:
generating a programming pattern for one of the programmable functionalities to be loaded into the reprogrammable structure.
26. The computer readable medium of claim 20 , wherein step (c) includes performing physical layout for the entire mask-programmed integrated circuit using a predefined array.
27. The computer readable medium of claim 26 , wherein the predefined array includes one of a module based array and a gate array.
28. The computer readable medium of claim 20 , wherein the reprogrammable structure is functionally equivalent to a PLA.