Patent Assignment
Reel/Frame 051464/0389
Assignment of Assignor's Interest
Recorded: 2020-01-03
Pages: 14
Assignor
CALLAHAN CELLULAR L.L.C.
Executed: 2019-12-23
Assignee
INTELLECTUAL VENTURES ASSETS 154 LLC
251 LITTLE FALLS DRIVE, WILMINGTON, DELAWARE, 19808
Covered Properties
(60)
Bridge State-Machine Progression for Data Transfers Requested by a Host Bus and Responded to by an External Bus
Patent:
6,477,609 →
Application:
09/495,043 →
Programmable Logic Array Embedded in Mask-Programmed Asic
Patent:
6,694,491 →
Application:
09/512,783 →
Accurate Power Detection Circuit for Use in a Power Amplifier
Patent:
6,448,855 →
Application:
09/548,726 →
Method and System for Proactively Debugging Fitting Problems in Programmable Logic Devices
Patent:
6,481,001 →
Application:
09/563,233 →
Programmable Number of Metal Lines and Effective Metal Width Along Critical Paths in a Programmable Logic Device
Patent:
6,476,635 →
Application:
09/604,992 →
Loadable Divide-by-N with Fixed Duty Cycle
Patent:
6,501,815 →
Application:
09/607,697 →
Low Noise Switching Regulator
Patent:
6,441,593 →
Application:
09/736,907 →
Low Noise, Reduced Swing Differential Output Buffer Design
Patent:
6,529,036 →
Application:
09/742,758 →
Laser Formation of a Metal Capacitor and Integrated Coaxial Line
Patent:
6,465,732 →
Application:
09/792,021 →
Buffer Improvement
Patent:
6,504,413 →
Application:
09/813,572 →
Depopulated Programmable Logic Array
Active Termination Circuit with an Enable/Disable
Programmable Logic Array Embedded in Mask-Programmed Asic
Function Block Architecture with Variable Drive Strengths
Patent:
6,696,856 →
Application:
10/020,469 →
Field Programmable Gate Array with Convertibility to Application Specific Integrated Circuit
Semiconductor Switching Devices
Semiconductor Latches and Sram Devices
Depopulated Programmable Logic Array
Implementing Programmable Logic Array Embedded in Mask - Programmed Asic
Insulated-Gate Field-Effect Thin Film Transistors
Semiconductor Latches and Sram Devices
Programmable Devices with Convertibility to Customizable Devices
Semiconductor Latches and Sram Devices
Methods for Fabricating Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Semiconductor Latches and Sram Devices
Semiconductor Devices Fabricated with Different Processing Options
Alterable Application Specific Integrated Circuit (Asic)
Semiconductor Switching Devices
Three Dimensional Integrated Circuits
Insulated-Gate Field-Effect Thin Film Transistors
Configuration Circuits for Three Dimensional Programmable Logic Devices
Methods for Fabricating Fuse Programmable Three Dimensional Integrated Circuits
Configuration Circuit for Programmable Logic Devices
Three dimensional integrated circuits
Configuration Circuits for Programmable Logic Devices
Timing Exact Design Conversions from Fpga to Asic
Alterable Application Specific Integrated Circuit (Asic)
Bit Stream Compatible Fpga to Mpga Design Conversions
Semiconductor Devices Fabricated with Different Processing Options
Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Alterable Application Specific Integrated Circuit (Asic)
Timing Exact Design Conversions from FPGA to ASIC
Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Mpga Products Based on a Prototype Fpga
Patent:
45,110 →
Application:
13/411,486 →
Three Dimensional Integrated Circuits
Timing Exact Design Conversions from Fpga to Asic
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Timing Exact Design Conversions from Fpga to Asic
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Application:
16/422,942 →
Publication:
US 2019/0279993
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Merger
Sep 29, 2015
From: SOKIA MGMT. LIMITED LIABILITY COMPANY
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 036711/0530 →
Merger
Oct 9, 2015
From: YAKIMISHU CO. LTD., L.L.C.
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 036829/0821 →
Merger
Jan 6, 2016
From: OTRSOTECH, LIMITED LIABILITY COMPANY
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 037451/0611 →
Partial Release of Security Interest in Patents
Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest
Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
Assignment of Assignor's Interest
Jan 27, 2020
From: INTELLECTUAL VENTURES ASSETS 154 LLC
To: LIBERTY PATENTS LLC
Reel/Frame 051709/0805 →
Corrective Assignment to Correct the 8647899 Previously Recorded on Reel 035240 Frame 0429. Assignor(S) Hereby Confirms the Security Interst.
Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
Patent Security Agreement
May 1, 2023
From: RPX CORPORATION
To: BARINGS FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 063503/0742 →