Three dimensional integrated circuits
View Patent ↗A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
1. A three-dimensional semiconductor device, comprising:
a first module layer having a plurality of circuit blocks; and
a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and
a third module layer positioned substantially above the first module layer, including a plurality of circuit blocks, further including one or more of programmable multiplexer logic elements;
wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers and wherein the first module layer comprises one or more of programmable pass-gate, programmable multiplexer and programmable inverter logic elements.
2. The device of claim 1 , wherein the configuration circuits comprise memory elements.
3. The device of claim 2 , wherein the memory element is one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tubes, mask programmable elements and any other memory element.
4. The device of claim 2 , wherein the memory elements further comprises one or more redundant memory elements to control the same circuit block.
5. The device of claim 1 , wherein the configuration circuit comprises random access memory (RAM) elements that provide user configurability or a predetermined metal wire pattern that provide customized mask configurability to control the circuit blocks.
6. The device of claim 1 , further comprising a fourth module layer formed in between the second and third module layer, and a fifth module layer formed substantially above the third module layer, wherein interconnect and routing signals are formed to connect the circuit blocks within the first, second and third module layers.
7. The device of claim 1 , further comprising a fourth module layer formed in between the first and second module layer, a fifth module layer formed in between the second and third module layers and a sixth module layer formed above the third module layer, wherein interconnect and routing signals are formed to connect the circuit blocks within the first, second and third module layers.
8. The device of claim 1 , wherein the circuit blocks in the first module layer further comprises of programmable logic blocks which responds to input control signals from the configuration circuits in the second module and develop corresponding complete or partial output logic signals, and registers to store the logic signals and either outputting them to output terminals or returning them as inputs to additional programmable logic blocks.
9. The device of claim 1 , wherein the circuit blocks in the third module layer further comprises of programmable multiplexers which responds to input control signals from the configuration circuits in the second module and develop corresponding wire to wire connection patterns.
10. The device of claim 8 , wherein the programmable logic block is selected from one or more of pass gate logic, multiplexer logic, inverter logic, look up table (LUT) logic and AND/OR logic.
11. A multi-dimensional semiconductor device, comprising:
a plurality of programmable logic blocks formed on a first module layer comprising a semiconductor substrate; and
a plurality of configuration circuits including memory elements formed on a second module layer comprising a semiconductor thin film layer, said second module layer deposited substantially above the first module layer; and
a plurality of programmable multiplexer (MUX) circuits formed on a third module layer comprising a semiconductor thin film layer, said third module layer deposited substantially above the first module layer;
wherein, the data stored in memory elements of the configuration circuits fully program the programmable logic content in the first module layer, and the programmable MUX connections in the third module layer.
12. The device of claim 11 , wherein the configuration circuit comprises user configurable random access memory elements for the user to store modifiable binary data values to program the device.
13. The device of claim 11 , wherein the configuration circuits comprises mask configurable hard-wire connection pattern for the user to couple ground and power supply voltages as permanent binary data values to program the device.
14. The device of claim 13 , wherein the programmable MUX circuits are further replaceable by another mask configurable hard-wire connection pattern in lieu of the thin-film MUX module, and wherein:
every input and output to the thin-film MUX module is replaced by an isolated metal tab; and
every input to output on path in the thin-film MUX module is further replaced by a metal link coupling the corresponding two tabs.
15. The device of claim 11 , wherein the memory element is one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tubes, mask programmable elements and any other memory element.