Patent Assignment
Reel/Frame 051709/0805
Assignment of Assignor's Interest
Recorded: 2020-01-27
Pages: 13
Assignor
INTELLECTUAL VENTURES ASSETS 154 LLC
Executed: 2019-12-30
Assignee
LIBERTY PATENTS LLC
2325 OAK ALLEY, TYLER, TEXAS, 75703
Covered Properties
(82)
Bridge State-Machine Progression for Data Transfers Requested by a Host Bus and Responded to by an External Bus
Patent:
6,477,609 →
Application:
09/495,043 →
Programmable Logic Array Embedded in Mask-Programmed Asic
Patent:
6,694,491 →
Application:
09/512,783 →
Flash Cell Device
Patent:
6,563,166 →
Application:
09/523,064 →
Accurate Power Detection Circuit for Use in a Power Amplifier
Patent:
6,448,855 →
Application:
09/548,726 →
Method and System for Proactively Debugging Fitting Problems in Programmable Logic Devices
Patent:
6,481,001 →
Application:
09/563,233 →
Track/Attenuate Circuit and Method for Switched Current Source Dac
Patent:
6,417,793 →
Application:
09/578,838 →
Cache Memory Array for Multiple Address Spaces
Patent:
6,571,316 →
Application:
09/595,077 →
Programmable Number of Metal Lines and Effective Metal Width Along Critical Paths in a Programmable Logic Device
Patent:
6,476,635 →
Application:
09/604,992 →
Loadable Divide-by-N with Fixed Duty Cycle
Patent:
6,501,815 →
Application:
09/607,697 →
Self-trimming current source and method for switched current source DAC
Patent:
6,331,830 →
Application:
09/631,596 →
Method for Preventing Native Oxide Growth During Nitridation
Patent:
6,495,476 →
Application:
09/642,939 →
Programmable non-overlap time output driver
Patent:
6,339,348 →
Application:
09/660,449 →
Intergrated Circuit Capable of Operating at Two Different Power Supply Voltages
Patent:
6,468,860 →
Application:
09/713,813 →
Low Noise Switching Regulator
Patent:
6,441,593 →
Application:
09/736,907 →
Low Noise, Reduced Swing Differential Output Buffer Design
Patent:
6,529,036 →
Application:
09/742,758 →
Laser Formation of a Metal Capacitor and Integrated Coaxial Line
Patent:
6,465,732 →
Application:
09/792,021 →
Surface Acoustic Wave Filter Device Having a Signal Line Connected by a Wire to a Floating Electrode
Buffer Improvement
Patent:
6,504,413 →
Application:
09/813,572 →
Depopulated Programmable Logic Array
Active Termination Circuit with an Enable/Disable
Energy-Conserving Apparatus and Operating System Having Multiple Operating Functions Stored in Keep-Alive Memory
Programmable Logic Array Embedded in Mask-Programmed Asic
Memory Cell Having a Deep Trench Capacitor and a Vertical Channel
Patent:
6,479,852 →
Application:
09/983,681 →
Assembly with Connecting Structure
Enhanced Zdb Feedback Methodology Utilizing Binary Weighted Techniques
Patent:
6,608,530 →
Application:
10/017,709 →
Function Block Architecture with Variable Drive Strengths
Patent:
6,696,856 →
Application:
10/020,469 →
Substrate for Semiconductor Package
Method for Generating Register Transfer Level Code
Field Programmable Gate Array with Convertibility to Application Specific Integrated Circuit
Electrostatic Discharge Protection Device for Giga-Hertz Radio Frequency Integrated Circuits with Varactor-Lc Tanks
Semiconductor Switching Devices
Semiconductor Latches and Sram Devices
Depopulated Programmable Logic Array
Method for Increasing the Speed of Speculative Execution
Patent:
7,337,439 →
Application:
10/464,871 →
Enhanced Zdb Feedback Methodology Utilizing Binary Weighted Techniques
Patent:
6,734,740 →
Application:
10/639,342 →
Implementing Programmable Logic Array Embedded in Mask - Programmed Asic
Insulated-Gate Field-Effect Thin Film Transistors
Semiconductor Latches and Sram Devices
Programmable Devices with Convertibility to Customizable Devices
Semiconductor Latches and Sram Devices
Methods for Fabricating Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Semiconductor Latches and Sram Devices
Semiconductor Devices Fabricated with Different Processing Options
Alterable Application Specific Integrated Circuit (Asic)
Embedded System and Related Method Capable of Automatically Updating System Software
Semiconductor Switching Devices
Three Dimensional Integrated Circuits
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Patent:
7,509,504 →
Application:
10/956,219 →
Insulated-Gate Field-Effect Thin Film Transistors
Configuration Circuits for Three Dimensional Programmable Logic Devices
Methods for Fabricating Fuse Programmable Three Dimensional Integrated Circuits
Translated Memory Protection Apparatus for an Advanced Microprocessor
Patent:
8,055,877 →
Application:
11/248,813 →
Configuration Circuit for Programmable Logic Devices
Three dimensional integrated circuits
Configuration Circuits for Programmable Logic Devices
Timing Exact Design Conversions from Fpga to Asic
Alterable Application Specific Integrated Circuit (Asic)
Bit Stream Compatible Fpga to Mpga Design Conversions
Semiconductor Devices Fabricated with Different Processing Options
Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Alterable Application Specific Integrated Circuit (Asic)
Timing Exact Design Conversions from FPGA to ASIC
Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Three Dimensional Integrated Circuits
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Mpga Products Based on a Prototype Fpga
Patent:
45,110 →
Application:
13/411,486 →
Three Dimensional Integrated Circuits
Timing Exact Design Conversions from Fpga to Asic
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Timing Exact Design Conversions from Fpga to Asic
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Pads and Pin-Outs in Three Dimensional Integrated Circuits
Application:
16/422,942 →
Publication:
US 2019/0279993
Related Assignments
(22)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Apr 23, 2012
From: LAPIS SEMICONDUCTOR CO., LTD.
To: INTELLECTUAL VENTURES FUND 77 LLC
Reel/Frame 028093/0534 →
Assignment of Assignor's Interest
Jul 9, 2012
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: ADZUKI FOUNDATION PTE. LLC
Reel/Frame 028510/0683 →
Security Interest
Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Merger
Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →
Merger
Sep 29, 2015
From: SOKIA MGMT. LIMITED LIABILITY COMPANY
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 036711/0530 →
Corrective Assignment to Correct the Assignor's Name Previously Recorded at Reel: 036711 Frame: 0160. Assignor(S) Hereby Confirms the Merger.
Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
Merger
Oct 9, 2015
From: OVERSTAM WIRELESS L.L.C.
To: OL SECURITY LIMITED LIABILITY COMPANY
Reel/Frame 036767/0365 →
Merger
Jan 6, 2016
From: OTRSOTECH, LIMITED LIABILITY COMPANY
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 037451/0611 →
Merger
Jan 22, 2016
From: OTROSANI ASSET MGMT. L.L.C.
To: OL SECURITY LIMITED LIABILITY COMPANY
Reel/Frame 037563/0730 →
Merger
Jan 22, 2016
From: SCHILMASS CO. L.L.C.
To: GULA CONSULTING LIMITED LIABILITY COMPANY
Reel/Frame 037559/0856 →
Merger
Jan 22, 2016
From: ADZUKI FOUNDATION PTE. LLC
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 037563/0896 →
Merger
Jan 25, 2016
From: INTELLECTUAL VENTURES FUND 77 LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 037577/0581 →
Partial Release of Security Interest in Patents
Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest
Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
Assignment of Assignor's Interest
Aug 13, 2018
From: LOCKHEED MARTIN CORPORATION
To: BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.
Reel/Frame 046625/0568 →
Assignment of Assignor's Interest
Jan 3, 2020
From: OL SECURITY LIMITED LIABILITY COMPANY
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051412/0813 →
Assignment of Assignor's Interest
Jan 3, 2020
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051411/0565 →
Assignment of Assignor's Interest
Jan 3, 2020
From: GULA CONSULTING LIMITED LIABILITY COMPANY
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051411/0491 →
Assignment of Assignor's Interest
Jan 3, 2020
From: CHANG LIAO HOLDINGS, LLC
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051411/0344 →
Assignment of Assignor's Interest
Jan 3, 2020
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051464/0389 →
Assignment of Assignor's Interest
Jan 3, 2020
From: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051413/0171 →
Corrective Assignment to Correct the 8647899 Previously Recorded on Reel 035240 Frame 0429. Assignor(S) Hereby Confirms the Security Interst.
Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →