Configuration circuit for programmable logic devices

1. A configuration circuit for a programmable logic device, comprising:

a first voltage, a second voltage at a lower level than the first voltage, and a third voltage at a lower level than the second voltage; and

a memory circuit to store one or more data values coupled between the first and third voltages,

said memory circuit comprising:

a configurable means to alter the stored data values; and

one or more outputs; and

a voltage conversion device coupled between the second and third voltages, and further coupled to said one or more outputs of the memory circuit, wherein said voltage conversion device generates a digital control signal either at the second voltage level or the third voltage level.

2. The circuit of claim 1 , wherein the third voltage is preferably at a system ground voltage level and more preferably at zero voltage level.

3. The circuit of claim 1 , wherein the first voltage is at a first system power voltage level in the range 1.8 volts to 10.0 volts, and wherein the second voltage is at a second system power voltage level in the range 0.5 volts to 1.8 volts.

4. The circuit of claim 1 , wherein the memory circuit comprises memory elements further comprising one of: fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tube elements, optical elements, mask programmable elements and any other memory element.

5. The circuit of claim 1 , wherein the memory circuit further comprises a random access memory (RAM) element, and wherein the configurable means further comprises:

an access device to the RAM element; and

a decoding circuit to select the RAM bit and alter the stored data polarity, whereby said digital control signal can be configured between the second voltage level or the third voltage level by altering the stored data polarity.

6. The circuit of claim 1 , wherein the control signal is coupled to a programmable logic circuit operating at a power voltage level equal to or less than the second voltage level.

7. The circuit of claim 1 , wherein the memory circuit further comprises:

the stored data value comprising a first and a second data polarity; and

the one or more outputs comprising a first and a second output, wherein:

the first output is at the third voltage for the first data polarity, and at the first voltage for the second data polarity; and

the second output is at the first voltage for the first data polarity, and at the third voltage for the second data polarity.

8. The circuit of claim 7 , wherein the voltage conversion device comprises:

a first NMOSFET device wherein the source is coupled to the third voltage, the drain is coupled to the control signal and the gate is coupled to the first output; and

a second NMOSFET device wherein the drain is coupled to the second voltage, the source is coupled to the control signal and the gate is coupled to the second output.

9. The circuit of claim 8 , wherein the memory circuit and the voltage conversion device comprises thin film transistors (TFT) comprising low mobility amorphous or polycrystalline silicon material, and wherein using a first voltage higher than the second voltage improves the TFT drive current while limiting the control signal voltage level to the second voltage.

10. The circuit of claim 1 , wherein the memory circuit further comprises a read only memory (ROM) element, and wherein the configurable means is further comprised of:

a mask fabrication process step, wherein said control signal is configured between the second voltage level or the third voltage level by coupling the control signal to the third voltage or coupling the control signal to the second voltage.

11. A semiconductor device, comprising:

a configuration circuit comprised of:

a configurable memory circuit, said circuit comprising a logic one state at a first voltage level; and

a voltage conversion circuit coupled to the memory circuit, said circuit generating a configurable digital control signal, said control signal comprising a logic one state at a second voltage level lower than said first voltage level; and

a digital programmable logic circuit coupled to said control signal to program the logic circuit, said logic circuit further comprising a logic one state at a third voltage level lower than said second voltage level.

12. The device of claim 11 , wherein:

the digital programmable logic circuit is in a first module layer; and

the configuration circuit is in a second module layer positioned substantially above the first module layer.

13. The device of claim 11 , wherein the configuration circuit comprises a thin film transistor.

14. The device of claim 13 , wherein the thin film transistor (TFT) further comprises:

a thin film semiconductor material comprising a lower mobility than a silicon substrate material, wherein the first voltage improves the conduction current of the TFT transistor while limiting the control signal to the second voltage level.

15. The device of claim 11 , wherein the memory circuit comprises memory elements further comprising one of: fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tube elements, optical elements, mask programmable elements and any other memory element.

16. The device of claim 11 , wherein the configurable memory circuit and the voltage conversion circuit and the digital programmable logic circuit comprises a logic zero state, said logic zero state at a system ground voltage level.

17. The device of claim 16 , wherein the memory circuit comprises a configurable memory element, and wherein the configurable digital control signal is configured to the logic one state or the logic zero state by configuring the memory element.

18. The device of claim 16 , wherein the memory circuit further comprises:

a static random access memory (SRAM) cell, said SRAM cell coupled to the first voltage and the system ground voltage, said SRAM cell comprising one or more access transistors to configure the stored data polarity between a first state and a second state, said SRAM cell further comprising a first and a second output, wherein:

the first output is at the ground voltage for the first data state, and at the first voltage for the second data state; and

the second output is at the first voltage for the first data state, and at the ground voltage for the second data state.

19. The device of claim 18 , wherein the voltage conversion circuit further comprises:

a first N-type carrier transistor wherein the source is coupled to the ground voltage, the drain is coupled to the control signal and the gate is coupled to the first output; and

a second N-type carrier transistor wherein the drain is coupled to the second voltage, the source is coupled to the control signal and the gate is coupled to the second output.

20. A configuration circuit, comprising:

a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and

a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to said output;

wherein, the voltage conversion circuit generates a configurable control signal either at the ground voltage level or the second voltage level by configuring the storage element.