IP Library Granted Patent US 7,446,563
Granted Patent B2
US 7,446,563 · App. 11/985,822 · Granted Nov 4, 2008

Three dimensional integrated circuits

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Quick Facts
Patent No.
US 7,446,563
App. No.
11/985,822
Granted
Nov 4, 2008
Kind
B2
Abstract

A programmable integrated circuit (IC), wherein: a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

Claims (29)

1. A mask configurable semiconductor device, comprising:

a programmable logic circuit having one or more high impedance nodes; and

a read only memory (ROM) element coupled to a said high impedance node to configure the programmable logic circuit, wherein the ROM element is positioned substantially above or below the programmable logic circuit.

2. The device of claim 1 , wherein the ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.

3. The device of claim 2 , wherein the ROM element is customized during the fabrication process, said customization comprised of:

identifying power or ground supply voltage connection to program the programmable logic circuit to said user specification, and

customizing at least one mask in the fabrication process to provide said power or ground supply voltage connection.

4. The device of claim 3 , wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.

5. The device of claim 1 , wherein interconnect and routing signals are positioned below the ROM element and above transistors of the programmable logic circuit.

6. The device of claim 1 , wherein interconnect and routing signals are positioned above the ROM element.

7. The device of claim 1 , wherein interconnect and routing signals are positioned above and below the ROM element.

8. A programmable semiconductor device, comprising:

a plurality of programmable pass-gate logic elements constructed on a semiconductor substrate layer; and

a plurality of read only memory (ROM) elements positioned substantially above or below the semiconductor substrate layer, a said ROM element coupled to a said programmable pass-gate logic element to program the pass-gate logic element to a user specification.

9. The device of claim 8 , wherein a said pass-gate logic element is configured by a digital input signal, the digital input signal generated by a said ROM element.

10. The device of claim 8 , wherein a said pass-gate logic element comprises a high-mobility semiconductor substrate transistor.

11. The device of claim 8 , wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.

12. The device of claim 11 , wherein the ROM element is customized during the fabrication process, said customization comprised of:

identifying power or ground supply voltage connection to program the programmable logic circuit to said user specification, and

customizing at least one mask in the fabrication process to provide said power or ground supply voltage connection.

13. The device of claim 12 , wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.

14. The device of claim 10 , wherein interconnect and routing signals are positioned below the ROM element and above the programmable pass-gate logic transistor.

15. The device of claim 8 , wherein interconnect and routing signals are positioned above the ROM element.

16. The device of claim 8 , wherein interconnect and routing signals are positioned above and below the ROM element.

17. A programmable integrated circuit (IC), wherein:

a programmable logic circuit is programmed to a user specification by configuring a transistor gate control signal generated by a read only memory (ROM) element positioned substantially above or below the transistor.

18. The IC of claim 17 , further comprising a plurality of programmable metal interconnects, wherein one or more metal interconnects is configured to a user specification by a said ROM element.

19. The IC of claim 17 , wherein the programmable logic circuit further comprises one or more digital inputs, a said digital input is configured to a user specification by a said ROM element.

20. The IC of claim 17 , wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage as identified by said user specification.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2020
From: INTELLECTUAL VENTURES ASSETS 154 LLC
To: LIBERTY PATENTS LLC
Reel/Frame 051709/0805 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2020
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051464/0389 →
MERGER Recorded Oct 9, 2015
From: YAKIMISHU CO. LTD., L.L.C.
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 036829/0821 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2011
From: MADURAWE, RAMINDA U.
To: VICICIV TECHNOLOGY, INC.
Reel/Frame 026868/0831 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2011
From: TIER LOGIC, INC.
To: YAKIMISHU CO. LTD., LLC
Reel/Frame 026839/0396 →
CHANGE OF NAME Recorded Aug 29, 2011
From: VICICIV TECHNOLOGY, INC.
To: TIER LOGIC, INC.
Reel/Frame 026824/0623 →