Three dimensional integrated circuits

1. A mask configurable semiconductor device, comprising:

a first module layer having programmable logic elements comprised of:

a plurality of pass-gate logic elements, each element connecting a first node to a second node, each element comprising a programmable gate-signal, said gate-signal either at logic one to connect said first node to second node or at logic zero to disconnect said first node from second node; and

a plurality of inverter logic elements, each element comprising a programmable input-signal and an output, each said output providing a truth table value, each said input-signal either at logic one to generate a zero truth table value or at logic zero to generate a one truth table value;

a second module layer positioned substantially above the first module layer, including a read only memory (ROM) configuration circuit to program said programmable logic elements in the first module to a user specification.

2. The device of claim 1 , wherein the first module layer comprises a semiconductor substrate layer.

3. The device of claim 2 , wherein each of said pass-gate logic elements and the inverter logic elements is comprised of high-mobility substrate transistors.

4. The device of claim 1 , wherein the ROM configuration circuit comprises a ROM element comprised of either a wire connected to power supply voltage or a wire connected to ground supply voltage.

5. The device of claim 4 , wherein the ROM configuration circuit is customized during the fabrication process, said customization method further comprised of:

identifying logic one and logic zero data levels required to program the programmable logic blocks to said user specification; and

identifying a power and ground supply voltage connection pattern to generate said logic one and said logic zero data levels respectively, and

customizing at least one mask in the fabrication process to provide said power and ground supply voltage connection pattern.

6. The device of claim 5 , wherein said at least one custom mask comprises a metal mask or a thin-hole mask in a multi-metal fabrication process.

7. The device of claim 1 further comprising a third module layer deposited in between the first and second module layer, wherein interconnect and routing signals are formed to connect the circuit blocks within the first and second module layers.

8. The device of claim 1 further comprising a third module layer deposited above the first and second module layer, wherein interconnect and routing signals are formed to connect the circuit blocks within the first and second module layers.

9. The device of claim 8 , wherein the second module layer is integrated into the third module layer.

10. The device of claim 1 further comprising third and fourth module layers positioned above and below the second module layer respectively, wherein the third and fourth module layers provide interconnect and routing signals to connect the circuit blocks within the first and second module layers.

11. The device of claim 1 , wherein the programmable logic elements in said first module are assembled to provide one or more logic functions comprised of: look-up-table logic, point to point switch logic, multiplexer logic, truth table logic and AND/OR logic.

12. A programmable integrated circuit, comprising:

a first module layer having a plurality of programmable logic elements and further comprising one or more inverters in said first module, each said inverter comprising an input and an output; and

a second module layer positioned substantially above the first module layer, including a read only memory (ROM) configuration circuit to program said programmable logic elements in the first module to a user specification, wherein the inputs to a portion of said inverters are further controlled by the ROM configuration circuit.

13. The circuit of claim 12 , further comprising one or more transistors in said first module, wherein the transistor gate signals to a portion of said transistors are controlled by the ROM configuration circuit.

14. The circuit of claim 12 , wherein the ROM configuration circuit is constructed by metal wires connected to either power or ground supply voltages as identified by said user logic specification.