Patent Assignment
Reel/Frame 036711/0160
Merger
Recorded: 2015-09-29
Pages: 27
Assignor
INTELLECTUAL VENTURE FUNDING LLC
Executed: 2015-08-27
Assignee
INTELLECTUAL VENTURES HOLDING 81 LLC
7251 W LAKE MEAD BLVD, STE 300, LAS VEGAS, NEVADA, 89128
Covered Properties
(341)
Address Translation Method and Mechanism Using Physical Address Information Including During a Segmentation Process
Patent:
5,895,503 →
Application:
08/458,479 →
Combining Hardware and Software to Provide an Improved Microprocessor
Patent:
6,031,992 →
Application:
08/678,541 →
Host Microprocessor with Apparatus for Temporarily Holding Target Processor State
Patent:
5,958,061 →
Application:
08/685,721 →
A Memory Controller for a Microprocessor for Detecting a Failure of Speculation on the Physical Nature of a Component Being Addressed
Patent:
5,832,205 →
Application:
08/700,302 →
Translated Memory Protection Apparatus for an Advanced Microprocessor
Patent:
6,199,152 →
Application:
08/702,771 →
Nethod and Apparatus for Aliasing Memory Data in an Advanced Microprocessor
Patent:
5,926,832 →
Application:
08/721,698 →
A Gated Store Buffer for an Advanced Microprocessor
Patent:
6,011,908 →
Application:
08/772,686 →
Method and Apparatus for Correcting Errors in Computer Systems
Patent:
5,905,855 →
Application:
08/807,542 →
Address translation mechanism and method in a computer system
Patent:
6,226,733 →
Application:
08/905,356 →
Method and Apparatus for Enhancing Scheduling in an Advanced Microprocessor
Patent:
7,089,404 →
Application:
09/332,338 →
Memory Array Bitline Timing Circuit
Patent:
6,172,925 →
Application:
09/333,178 →
Method for Switching Between Interpretation and Dynamic Translation in a Processor System Based Upon Code Sequence Execution Counts
Patent:
7,761,857 →
Application:
09/417,332 →
Fine Grain Translation Discrimination
Patent:
6,363,336 →
Application:
09/417,356 →
System for Using Rate of Exception Event Generation During Execution of Translated Instructions to Control Optimization of the Translated Instructions
Patent:
6,714,904 →
Application:
09/417,358 →
Method of Optimizing Compiler Vs Interpreter Mode Operation in a Code Translator Based Upon Amount of Time Spent in Each Mode
Patent:
6,880,152 →
Application:
09/417,979 →
Method for Translating Instructions in a Speculative Microprocessor Featuring Committing State
Patent:
6,990,658 →
Application:
09/417,980 →
Method and Apparatus for Maintaining Context While Executing Translated Instructions
Patent:
6,415,379 →
Application:
09/417,981 →
Pipeline Replay Support for Unaligned Memory Operations
Patent:
6,728,865 →
Application:
09/420,748 →
Method for Increasing the Speed of Speculative Execution
Patent:
6,748,589 →
Application:
09/421,484 →
Electrostatic Discharge Protection for Mosfets
Use of Enable Bits to Control Execution of Selected Instructions
Patent:
6,738,892 →
Application:
09/421,615 →
Pipeline Replay Support for Multi-Cycle Operations Wherein All Vliw Instructions Are Flushed Upon Detection of a Multi-Cycle Atom Operation in a Vliw Instruction
Patent:
6,604,188 →
Application:
09/421,972 →
Instruction Packing for an Advanced Microprocessor
Patent:
6,754,892 →
Application:
09/464,638 →
Check Instruction and Method
Patent:
6,513,110 →
Application:
09/464,644 →
Software Direct Memory Access
Patent:
6,668,287 →
Application:
09/464,661 →
Interpage Prologue to Protect Virtual Address Mappings
Patent:
6,845,353 →
Application:
09/471,447 →
Adaptive Power Control
Translation Consistency Checking for Modified Target Instructions by Comparing to Original Copy
Patent:
6,594,821 →
Application:
09/539,987 →
Method and Apparatus for Scheduling to Reduce Space and Increase Speed of Microprocessor Operations
Patent:
6,738,893 →
Application:
09/557,650 →
Cache Memory Array for Multiple Address Spaces
Patent:
6,571,316 →
Application:
09/595,077 →
System and Method for Preserving Internal Processor Context When the Processor Is Powered Down and Restoring the Internal Processor Context When Processor Is Restored
Patent:
6,968,469 →
Application:
09/595,198 →
Method and Apparatus for Emulating a Floating Point Stack in a Translation Process
Patent:
6,725,361 →
Application:
09/595,199 →
Fast Look-Up of Indirect Branch Destination in a Dynamic Translation System
Patent:
6,615,300 →
Application:
09/596,279 →
Link Pipe System for Storage and Retrieval of Sequences of Branch Addresses
Patent:
6,640,297 →
Application:
09/596,280 →
Floating Point Exception Handling in Pipelined Processor Using Special Instruction to Detect Generated Exception and Execute Instructions Singly from Known Correct State
Patent:
6,826,682 →
Application:
09/603,743 →
Saving Power When in or Transitioning to a Static Mode of a Processor
Patent:
7,260,731 →
Application:
09/694,433 →
Translated Memory Protection Apparatus for an Advanced Microprocessor
Patent:
7,840,776 →
Application:
09/699,947 →
Method and Apparatus for Accelerating Fault Handling
Method and Apparatus for Handling Nested Faults
Method and Apparatus for Improving Segmented Memory Addressing
System and Method for Measuring Transistor Leakage Current with a Ring Oscillator
Patent:
6,882,172 →
Application:
10/124,152 →
Apparatus for Controlling Semiconductor Chip Characteristics
Patent:
7,472,033 →
Application:
10/273,681 →
Dynamic Node Keeper System and Method
Patent:
6,940,314 →
Application:
10/334,264 →
Diagonal Deep Well Region for Routing Body-Bias Voltage for Mosfets in Surface Well Regions
Software Controlled Transistor Body Bias
Adaptive Power Control Based on Pre Package Characterization of Integrated Circuits
Adaptive Power Control
Adaptive Power Control Based on Post Package Characterization of Integrated Circuits
Method and System for Using External Storage to Amortize Cpu Cycle Utilization
Patent:
7,444,471 →
Application:
10/335,405 →
Method and System for Using Idiom Recognition During a Software Translation Process
Patent:
7,203,932 →
Application:
10/335,459 →
Methods and Systems Employing a Flag for Deferring Exception Handling to a Commit or Rollback Point
Patent:
7,310,723 →
Application:
10/406,022 →
System and Method for Handling Direct Memory Accesses
Patent:
7,636,815 →
Application:
10/411,168 →
System for on-Chip Temperature Measurement in Integrated Circuits
Patent:
7,118,273 →
Application:
10/411,955 →
Translated Memory Protection Apparatus for an Advanced Microprocessor
Patent:
7,716,452 →
Application:
10/438,158 →
Temperature Compensated Integrated Circuits
Patent:
6,930,534 →
Application:
10/439,659 →
Voltage Compensated Integrated Circuits
Patent:
6,831,494 →
Application:
10/439,665 →
Pipeline Replay Support for Unaligned Memory Operations
Patent:
7,134,001 →
Application:
10/463,223 →
Fast Look-Up of Indirect Branch Destination in a Dynamic Translation System
Patent:
7,111,096 →
Application:
10/463,233 →
Pipeline Replay Support for Multi-Cycle Operations
Patent:
7,685,403 →
Application:
10/463,820 →
Switching to Original Modifiable Instruction Copy Comparison Check to Validate Prior Translation When Translated Sub-Area Protection Exception Slows Down Operation
Patent:
7,096,460 →
Application:
10/463,846 →
Method for Increasing the Speed of Speculative Execution
Patent:
7,337,439 →
Application:
10/464,871 →
Methods and Systems for Maintaining Information for Locating Non-Native Processor Instructions When Executing Native Processor Instructions
Patent:
7,249,246 →
Application:
10/600,989 →
Method and System for Implementing a Floating Point Compare Using Recorded Flags
Patent:
7,039,792 →
Application:
10/607,480 →
Method and System for Providing Hardware Support for Memory Protection and Virtual Memory Address Translation for a Virtual Machine
Patent:
7,111,146 →
Application:
10/607,934 →
Method and System for Supporting Input/Output for a Virtual Machine
Patent:
7,694,301 →
Application:
10/609,158 →
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Patent:
7,089,397 →
Application:
10/613,801 →
Explicit Control of Speculation
Patent:
7,451,300 →
Application:
10/620,862 →
Supporting Speculative Modification in a Data Cache
Patent:
7,225,299 →
Application:
10/622,028 →
Method and System for Enforcing Consistent Per-Physical Page Cacheability Attributes
Patent:
7,062,631 →
Application:
10/623,021 →
Method and System for Using One or More Address Bits and an Instruction to Increase an Instruction Set
Patent:
7,606,997 →
Application:
10/623,101 →
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Method and System for Conservatively Managing Store Capacity Available to a Processor Issuing Stores
Patent:
7,149,851 →
Application:
10/646,461 →
System and Method of Instruction Modification
Patent:
7,698,539 →
Application:
10/672,790 →
System and Method for Measuring Transistor Leakage Current with a Ring Oscillator with Backbias Controls
Patent:
6,885,210 →
Application:
10/672,793 →
System with Secure Cryptographic Capabilities Using a Hardware Specific Digital Secret
Patent:
7,681,046 →
Application:
10/672,796 →
Layout Patterns for Deep Well Region to Facilitate Routing Body-Bias Voltage
Patent:
7,098,512 →
Application:
10/683,732 →
Variable Output Charge Pump Circuit
Patent:
8,350,616 →
Application:
10/712,522 →
System for Substrate Potential Regulation During Power-Up in Integrated Circuits
Patent:
7,642,835 →
Application:
10/712,523 →
Device Aging Determination Circuit
Patent:
6,903,564 →
Application:
10/712,847 →
Method and System for Automatically Calibrating Intra-Cycle Timing Relationships for Sampling Signals for an Integrated Circuit Device
Patent:
7,646,835 →
Application:
10/716,320 →
Architecture, System, and Method for Operating on Encrypted and /or Hidden Information
Patent:
7,694,151 →
Application:
10/719,879 →
Servo Loop for Well Bias Voltage Source
Patent:
7,129,771 →
Application:
10/747,015 →
Feedback-Controlled Body-Bias Voltage Source
Patent:
7,649,402 →
Application:
10/747,016 →
Stabilization Component for a Substrate Potential Regulation Circuit
Patent:
7,012,461 →
Application:
10/747,022 →
Selective Coupling of Voltage Feeds for Body Bias Voltage in an Integrated Circuit Device
Patent:
7,332,763 →
Application:
10/765,316 →
Fractional Biasing of Semiconductors
Patent:
6,943,614 →
Application:
10/769,140 →
Systems and Methods for Adjusting Threshold Voltage
Patent:
7,205,758 →
Application:
10/771,015 →
Method for Generating a Deep N-Well Pattern for an Integrated Circuit Design
Patent:
7,645,673 →
Application:
10/772,029 →
Method and Apparatus for Enhancing Scheduling in an Advanced Microprocessor
Patent:
8,209,517 →
Application:
10/783,473 →
System and Method for Reducing Temperature Variation During Burn In
System and Method for Reducing Heat Dissipation During Burn-In
Patent:
6,897,671 →
Application:
10/791,241 →
System and Method for Controlling Temperature During Burn-In
Patent:
6,900,650 →
Application:
10/791,459 →
Deep Well Regions for Routing Body-Bias Voltage to Mosfets in Surface Well Regions Having Separation Wells of P-Type Between the Segmented Deep N Wells.
Patent:
7,759,740 →
Application:
10/808,225 →
Request Tracking Data Prefetcher Apparatus
Patent:
7,975,108 →
Application:
10/810,196 →
Structure for Spanning Gap in Body-Bias Voltage Routing Structure
Patent:
7,388,260 →
Application:
10/816,269 →
Use of Mtrr and Page Attribute Table to Support Multiple Byte Order Formats in a Computer System
Patent:
7,330,959 →
Application:
10/830,921 →
Stacked Inverter Delay Chain
Patent:
7,336,103 →
Application:
10/864,271 →
Voltage Compensated Integrated Circuits
Patent:
7,329,928 →
Application:
10/866,494 →
Inverting Zipper Repeater Circuit
Patent:
7,071,747 →
Application:
10/869,012 →
System and Method for Measuring Time Dependent Dielectric Breakdown with a Ring Oscillator
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
System and Method for Characterizing a Potential Distribution
Patent:
7,151,417 →
Application:
10/870,754 →
Adaptive Voltage Control by Accessing Information Stored Within and Specific to a Microprocessor
Patent:
7,774,625 →
Application:
10/874,407 →
Adaptive Control of Operating and Body Bias Voltages
Patent:
7,562,233 →
Application:
10/874,772 →
Repeater Circuit with High Performance Repeater Mode and Normal Repeater Mode, Wherein High Performance Repeater Mode Has Fast Reset Capability
Circuits and Methods for Detecting and Assisting Wire Transitions
Repeater Circuit Having Different Operating and Reset Voltage Ranges, and Methods Thereof
Repeater Circuit with High Performance Repeater Mode and Normal Repeater Mode
Exception Handling with Inserted Status Check Command Accommodating Floating Point Instruction Forward Move Across Branch
Patent:
7,337,307 →
Application:
10/938,091 →
Closed Loop Feedback Control of Integrated Circuits
Patent:
7,180,322 →
Application:
10/956,207 →
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Patent:
7,112,978 →
Application:
10/956,217 →
Systems and Methods for Integrated Circuits Comprising Multiple Body Bias Domains
Patent:
7,256,639 →
Application:
10/956,218 →
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Patent:
7,509,504 →
Application:
10/956,219 →
Systems and Methods for Integrated Circuits Comprising Multiple Body Biasing Domains
Patent:
7,859,062 →
Application:
10/956,722 →
System for on-Chip Temperature Measurement in Integrated Circuits
Patent:
7,108,420 →
Application:
10/961,311 →
Method and System for Tiling a Bias Design to Facilitate Efficient Design Rule Checking
Patent:
7,313,779 →
Application:
10/964,409 →
Method and System for Automated Schematic Diagram Conversion to Support Semiconductor Body Bias Designs
Patent:
7,496,868 →
Application:
10/964,448 →
Method and Apparatus for Handling Nested Faults
Patent:
7,640,450 →
Application:
10/980,127 →
Ring Based Impedance Control of an Output Driver
Patent:
7,330,080 →
Application:
10/981,964 →
Systems and Methods for Voltage Distribution via Epitaxial Layers
Systems and Methods for Voltage Distribution via Multiple Epitaxial Layers
Circuits and Methods for Detecting and Assisting Wire Transitions
Patent:
7,295,041 →
Application:
11/005,762 →
Method and System for Configurable Contacts for Implementing Different Bias Designs of an Integrated Circuit Device
Patent:
7,802,223 →
Application:
11/018,880 →
Configurable Delay Chain with Stacked Inverter Delay Elements
Patent:
7,310,008 →
Application:
11/020,746 →
Leakage Efficient Anti-Glitch Filter with Variable Delay Stages
Patent:
7,332,931 →
Application:
11/021,197 →
Configurable Delay Chain with Switching Control for Tail Delay Elements
Patent:
7,656,212 →
Application:
11/021,221 →
Configurable Tapered Delay Chain with Multiple Sizes of Delay Elements
Patent:
7,635,992 →
Application:
11/021,222 →
Power Efficient Multiplexer
Patent:
7,498,846 →
Application:
11/021,632 →
Leakage Efficient Anti-Glitch Filter
Patent:
7,330,054 →
Application:
11/021,633 →
Method and Apparatus for Improving Segmented Memory Addressing
Patent:
7,334,109 →
Application:
11/026,623 →
Method and System for Validating a Computer System
Methods and Systems for Measuring Temperature Using Digital Signals
Patent:
7,212,064 →
Application:
11/056,549 →
Method for Translating Instructions in a Speculative Microprocessor
Patent:
7,694,113 →
Application:
11/069,497 →
System and Method for Measuring Transistor Leakage Current with a Ring Oscillator
Patent:
7,038,483 →
Application:
11/070,630 →
Method of Optimizing Compiler Vs Interpreter Mode Operation in a Code Translator Based Upon Amount of Time Spent in Each Mode
Patent:
7,331,041 →
Application:
11/077,623 →
Method and System for Elastic Signal Pipelining
System, Method and Circuits for Generating a Signal
Patent:
7,227,397 →
Application:
11/096,770 →
Memory Protection and Address Translation Hardware Support for Virtual Machines
Patent:
7,734,892 →
Application:
11/096,922 →
Memory Management Methods and Systems That Support Cache Consistency
Patent:
7,376,798 →
Application:
11/102,127 →
Coherence de-coupling buffer
Patent:
8,751,753 →
Application:
11/102,171 →
Maintaining Instruction Coherency in a Translation-Based Computer System Architecture
Patent:
7,971,002 →
Application:
11/102,538 →
Interpage Prologue to Protect Virtual Address Mappings
Patent:
7,617,088 →
Application:
11/110,085 →
Temperature Compensated Integrated Circuits
Patent:
7,495,497 →
Application:
11/125,555 →
Level shifter for noise and leakage suppression
Patent:
8,803,584 →
Application:
11/132,052 →
System and Method for Reducing Heat Dissipation During Burn-In
Patent:
7,242,205 →
Application:
11/136,038 →
System and Method for Controlling Temperature During Burn-In
Patent:
7,463,050 →
Application:
11/139,116 →
Method and System for Providing Trusted Access to a Jtag Scan Interface in a Microprocessor
Patent:
7,600,166 →
Application:
11/169,403 →
Multi-Threading Based on Rollback
Patent:
8,413,162 →
Application:
11/169,404 →
Clock Signal Distribution System and Method
Wire Mesh Patterns for Semiconductor Devices
Patent:
7,217,962 →
Application:
11/171,673 →
Scannable Dynamic Circuit Latch
Advanced Repeater Utilizing Signal Distribution Delay
Patent:
7,375,556 →
Application:
11/171,845 →
Advanced Repeater with Duty Cycle Adjustment
Patent:
7,405,597 →
Application:
11/172,013 →
Elastic Pipeline Latch with a Safe Mode
Using Standard Pattern Tiles and Custom Pattern Tiles to Generate a Semiconductor Design Layout Having a Deep Well Structure for Routing Body-Bias Voltage
Patent:
7,305,647 →
Application:
11/193,723 →
Diagonal Deep Well Region for Routing Body-Bias Voltage for Mosfets in Surface Well Regions
Patent:
7,211,478 →
Application:
11/199,896 →
Dynamic Node Keeper System and Method
Patent:
7,221,189 →
Application:
11/199,950 →
A System and Method for Saving and Restoring a Processor State Without Executing Any Instructions from a First Instruction Set
Patent:
7,730,330 →
Application:
11/201,624 →
Balanced Adaptive Body Bias Control
Patent:
7,949,864 →
Application:
11/238,446 →
Method and System for Protecting Processors from Unauthorized Debug Access
Method and System for Latchup Suppression
Patent:
7,786,756 →
Application:
11/241,552 →
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Patent:
7,315,178 →
Application:
11/248,440 →
Translated Memory Protection Apparatus for an Advanced Microprocessor
Patent:
8,055,877 →
Application:
11/248,813 →
System and Method for Measuring Time Dependent Dielectric Breakdown with a Ring Oscillator
Patent:
7,235,998 →
Application:
11/269,989 →
Column Select Multiplexer Circuit for a Domino Random Access Memory Array
Patent:
7,394,681 →
Application:
11/273,897 →
Non-Rectilinear Routing in Rectilinear Mesh of a Metallization Layer of an Intregrated Circuit
Patent:
7,755,193 →
Application:
11/274,098 →
Secure Memory Access System and Method
Patent:
7,496,727 →
Application:
11/296,591 →
Data Structure for Enforcing Consistent Per-Physical Page Cacheability Attributes
Patent:
7,676,629 →
Application:
11/314,494 →
Circuits, Systems and Methods Relating to Dynamic Ring Oscillators
Patent:
7,414,485 →
Application:
11/322,595 →
Circuits, Systems and Methods Relating to a Dynamic Dual Domino Ring Oscillator
Patent:
7,642,866 →
Application:
11/322,896 →
Stabilization Component for a Substrate Potential Regulation Circuit
Patent:
7,719,344 →
Application:
11/358,482 →
Conversion of an Soi Design Layout to a Bulk Design Layout
Patent:
7,579,221 →
Application:
11/393,555 →
Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
Patent:
8,522,253 →
Application:
11/394,521 →
Multi-Write Memory Circuit with a Data Input and a Clock Input
Techniques for Detecting and Correcting Errors in a Memory Device
Patent:
7,904,789 →
Application:
11/395,710 →
Multi-Write Memory Circuit with Multiple Data Inputs
Patent:
7,592,836 →
Application:
11/396,114 →
Systems and Methods for Integrated Circuits Comprising Multiple Body Biasing Domains
Patent:
7,816,742 →
Application:
11/400,368 →
Systems and Methods for Reordering Processor Instructions
Patent:
7,634,635 →
Application:
11/400,631 →
Adaptive Power Control
Patent:
7,596,708 →
Application:
11/411,309 →
Inverting Zipper Repeater Circuit
Patent:
7,646,228 →
Application:
11/435,692 →
System and Method for Handling Direct Memory Accesses
Patent:
7,620,779 →
Application:
11/439,361 →
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Patent:
7,380,096 →
Application:
11/449,950 →
Layout Pattern for Deep Well Region to Facilitate Routing Body-Bias Voltage
Patent:
7,645,664 →
Application:
11/449,952 →
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Patent:
7,380,098 →
Application:
11/454,355 →
Circuits and Methods for Detecting and Assisting Wire Transitions
Patent:
7,652,507 →
Application:
11/473,608 →
Double Diamond Clock and Power Distribution
Patent:
7,689,963 →
Application:
11/477,970 →
Processor modifications to increase computer system security
Patent:
8,661,265 →
Application:
11/479,486 →
Enhanced Clock Signal Flexible Distribution System and Method
Patent:
7,661,086 →
Application:
11/479,616 →
Cross Point Switch
Patent:
7,710,153 →
Application:
11/479,618 →
Dual Ported Replicated Data Cache
Patent:
7,747,896 →
Application:
11/479,630 →
Modifications to increase computer system security
Patent:
7,925,815 →
Application:
11/479,703 →
Triple Latch Flip Flop System and Method
Patent:
7,495,466 →
Application:
11/480,107 →
Closed Loop Feedback Control of Integrated Circuits
Patent:
7,336,092 →
Application:
11/490,356 →
Method and System for Providing Hardware Support for Memory Protection and Virtual Memory Address Translation for a Virtual Machine
Patent:
8,041,876 →
Application:
11/500,575 →
Switching to Original Code Comparison of Modifiable Code for Translated Code Validity When Frequency of Detecting Memory Overwrites Exceeds Threshold
Patent:
7,404,181 →
Application:
11/507,779 →
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Patent:
7,336,090 →
Application:
11/512,900 →
A Method and System for Storing and Retrieving a Translation of Target Program Instruction from a Host Processor Using Fast Look-Up of Indirect Branch Destination in a Dynamic Translation System
Patent:
7,644,210 →
Application:
11/524,044 →
System for on-Chip Temperature Measurement in Integrated Circuits
Application:
11/524,526 →
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Patent:
7,626,409 →
Application:
11/528,031 →
Dynamic Chip Control
Patent:
7,917,772 →
Application:
11/529,865 →
Raised Source/Drain with Super Steep Retrograde Channel
Patent:
7,683,442 →
Application:
11/529,972 →
Methods and Systems for Dynamically Changing Device Operating Conditions
Patent:
7,765,412 →
Application:
11/540,117 →
Signal Generator with Output Frequency Greater Than the Oscillator Frequency
Patent:
7,696,797 →
Application:
11/540,387 →
Processing Bypass Register File System and Method
Patent:
7,774,583 →
Application:
11/540,766 →
Processing Bypass Directory Tracking System and Method
Patent:
7,478,226 →
Application:
11/540,789 →
Braided Set Associative Caching Techniques
Patent:
7,725,656 →
Application:
11/583,463 →
Servo Loop for Well Bias Voltage Source
Patent:
7,362,165 →
Application:
11/591,431 →
Pipeline Replay Support for Unaligned Memory Operations
Patent:
7,886,135 →
Application:
11/594,672 →
Method and System for Conservatively Managing Store Capacity Available to a Processor Issuing Stores
Patent:
7,606,979 →
Application:
11/638,236 →
Systems and Methods for Determining Device Temperature
System and Method for Characterizing a Potential Distribution
Patent:
7,636,023 →
Application:
11/642,187 →
System Management Mode Code Modifications to Increase Computer System Security
Patent:
7,610,426 →
Application:
11/644,224 →
Repeater Circuit Having Different Operating and Reset Voltage Ranges, and Methods Thereof
Patent:
7,595,664 →
Application:
11/703,323 →
History Based Pipelined Branch Prediction
Patent:
7,779,241 →
Application:
11/786,336 →
Systems and Methods for Adjusting Threshold Voltage
Patent:
7,598,731 →
Application:
11/787,908 →
Diagonal Deep Well Region for Routing Body-Bias Voltage for Mosfets in Surface Well Regions
Patent:
7,323,367 →
Application:
11/799,496 →
Supporting Speculative Modification in a Data Cache
Patent:
7,873,793 →
Application:
11/807,629 →
Adaptive Power Control Based on Pre Package Characterization of Integrated Circuits
Patent:
8,442,784 →
Application:
11/810,516 →
System and Method for Reducing Heat Dissipation During Burn-In
Systems and Methods for Integrated Circuits Comprising Multiple Body Bias Domains
Patent:
7,782,110 →
Application:
11/880,351 →
System and Method for Reducing Temperature Variation During Burn In
Transitioning to and from a Sleep State of a Processor
Using Standard Pattern Tiles and Custom Pattern Tiles to Generate a Semiconductor Design Layout Having a Deep Well Structure for Routing Body-Bias Voltage
Patent:
7,797,655 →
Application:
11/999,279 →
Repeater Circuit with High Performance Repeater Mode and Normal Repeater Mode, Wherein High Performance Repeater Mode Has Fast Reset Capability
Setting a Flag Bit to Defer Event Handling to a Safe Point in an Instruction Stream
Patent:
8,019,983 →
Application:
12/002,983 →
Configurable Delay Chain with Stacked Inverter Delay Elements
A Method and System for a Tiling Bias Design to Facilitate Efficient Design Rule Checking
Patent:
8,099,689 →
Application:
12/005,018 →
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Sub-Surface Region with Diagonal Gap Regions
Supporting Multiple Byte Order Formats in a Computer System
Patent:
8,156,308 →
Application:
12/030,149 →
Voltage Compensated Integrated Circuits
Patent:
8,461,891 →
Application:
12/030,180 →
Method and Apparatus for Improving Segmented Memory Addressing
Patent:
7,725,677 →
Application:
12/033,784 →
Software Controlled Transistor Body Bias
Selective Coupling of Voltage Feeds for Body Bias Voltage in an Integrated Circuit Device
Method and System for Protecting Processors from Unauthorized Debug Access
Closed Loop Feedback Control of Integrated Circuits
Method for Increasing the Speed of Speculative Execution
Patent:
8,650,555 →
Application:
12/037,853 →
Checking for Exception by Floating Point Instruction Reordered Across Branch by Comparing Current Status in Fp Status Register Against Last Status Copied in Shadow Register
Patent:
7,840,788 →
Application:
12/037,872 →
Stacked Inverter Delay Chain
Pipeline Replay Support for Multicycle Operations
Patent:
8,117,423 →
Application:
12/042,224 →
Selective coupling of voltage feeds for body bias voltage in an integrated circuit device
Servo Loop for Well Bias Voltage Source
Patent:
7,847,619 →
Application:
12/107,733 →
Memory Management for Cache Consistency
Patent:
8,898,395 →
Application:
12/121,531 →
Advanced Repeater Utilizing Signal Distribution Delay
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Patent:
7,979,669 →
Application:
12/127,648 →
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Restoring Processor Context in Response to Processor Power-Up
Patent:
8,140,872 →
Application:
12/136,679 →
Structure for Spanning Gap in Body-Bias Voltage Routing Structure
Column Select Multiplexer Circuit for a Domino Random Access Memory Array
Patent:
7,679,949 →
Application:
12/165,432 →
Advanced Repeater with Duty Cycle Adjustment
Dynamic Ring Oscillators
Method and System for Using External Storage to Amortize Cpu Cycle Utilization
Patent:
7,925,855 →
Application:
12/259,262 →
Explicit Control of Speculation
Patent:
8,078,853 →
Application:
12/268,304 →
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Controlling Temperature in a Semiconductor Device
Patent:
7,834,648 →
Application:
12/330,324 →
Processing Bypass Directory Trancking System and Method
Patent:
7,937,566 →
Application:
12/353,064 →
Secure Memory Access System and Method
Patent:
7,966,467 →
Application:
12/391,998 →
Method and System for Automated Schematic Diagram Conversion to Support Semiconductor Body Bias Designs
Power Efficient Multiplexer
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Adaptive Power Control
Adaptive Control of Operating and Body Bias Voltages
System and Method for Reducing Temperature Variation During Burn In
Providing Trusted Access to a Jtag Scan Interface in a Microprocessor
Method for Generating a Deep N-Well Pattern for an Integrated Circuit Design
Circuit with Enhanced Mode and Normal Mode
Systems and Methods for Adjusting Threshold Voltage
Systems and Methods for Adjusting Threshold Voltage
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Architecure, System, and Method for Operating on Encrypted and/or Hidden Information
System Management and Advanced Programmable Interrupt Controller
Method for Integration of Interpretation and Translation in a Microprocessor
Handling Direct Memory Accesses
System for Substrate Potential Regulation During Power-Up in Integrated Circuits
System for Substrate Potential Regulation During Power-Up in Integrated Circuits
Inverting Zipper Repeater Circuit
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Closed Loop Feedback Control of Integrated Circuits
Feedback-Controlled Body-Bias Voltage Source
Data Structure for Enforcing Consistent Per-Physical Page Cacheability Attributes
System and Method of Instruction Modification
Signal Generator with Output Frequency Greater Than the Oscillator Frequency
Precise Control Component for a Substrate Potential Regulation Circuit
Cross Point Switch
Formation of a Super Steep Retrograde Channel
Translating Instructions in a Speculative Processor
Translated Memory Protection
Dual Ported Replicated Data Cache
History Based Pipelined Branch Prediction
Systems and Methods for Determining Device Temperature
Systems and Methods for Integrated Circuits Comprising Multiple Body Biasing Domains
Method and System for Configurable Contacts for Implementing Different Bias Designs of an Integrated Circuit Device
Systems and Methods for Integrated Circuits Comprising Multiple Body Biasing Domains
Saving Power When in or Transitioning to a Static Mode of a Processor
Supporting Speculative Modification in a Data Cache
Application:
13/007,015 →
Publication:
US 2015/0149733
Consistency Checking of Source Instruction to Execute Previously Translated Instructions Between Copy Made Upon Occurrence of Write Operation to Memory and Current Version
Ring Based Impedance Control of an Output Driver
Dynamic Chip Control
Method and System for Using External Storage to Amortize Cpu Cycle Utilization
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Processing Bypass Directory Tracking System and Method
Adaptive Power Control
Application:
13/103,952 →
Publication:
US 2011/0219245
Balanced Adaptive Body Bias Control
Application:
13/113,798 →
Publication:
US 2011/0221029
Adaptive Power Control Based on Post Package Characterization of Integrated Circuits
Application:
13/118,762 →
Publication:
US 2011/0231678
System and Method of Instruction Modification
Secure Memory Access System and Method
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Inverting Zipper Repeater Circuit
Software Controlled Transistor Body Bias
Formation of a Super Steep Retrograde Channel
Setting a Flag Bit to Defer Event Handling to One of Multiple Safe Points in an Instruction Stream
Signal Generator with Output Frequency Greater Than the Oscillator Frequency
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Advanced Repeater with Duty Cycle Adjustment
Method and System for Providing Hardware Support for Memory Protection and Virtual Memory Address Translation for a Virtual Machine
Translated Memory Protection Apparatus for an Advanced Microprocessor
System for on-Chip Temperature Measurement in Integrated Circuits
Power Efficient Multiplexer
Pipeline Replay Support for Multicycle Operations
Data Structure for Enforcing Consistent Per-Physical Page Cacheability Attributes
Storing Context Information Prior to Not Supplying Power to a Processor
Application:
13/370,241 →
Publication:
US 2012/0210155
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Supporting Multiple Byte Order Formats in a Computer System
Precise Control Component for a Substarate Potential Regulation Circuit
Method and Apparatus for Enhancing Scheduling in an Advanced Microprocessor
Processing Bypass Directory Tracking System and Method
Systems and Methods for Adjusting Threshold Voltage
Closed Loop Feedback Control of Integrated Circuits
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Secure Memory Access System and Method
Method and System for Providing Hardware Support for Memory Protection and Virtual Memory Address Translation for a Virtual Machine
Adaptive Power Control
Adaptive Control of Operating and Body Bias Voltages
Software Controlled Transistor Body Bias
Maintaining Processor Context Before Entering Power Saving Mode
Application:
13/950,495 →
Publication:
US 2013/0311802
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Patent:
8,924,648 →
Application:
14/033,314 →
Power Efficient Multiplexer
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Method for Increasing the Speed of Speculative Execution
Body-Bias Voltage Routing Structures
Coherence De-Coupling Buffer
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Corrective Assignment to Correct the Assignor's Name Previously Recorded at Reel: 036711 Frame: 0160. Assignor(S) Hereby Confirms the Merger.
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