Structure for spanning gap in body-bias voltage routing structure

1. A semiconductor device having a surface, comprising:

a plurality of conductive sub-surface regions of a first conductivity each formed beneath a well comprising a channel of said semiconductor device and each buried at a depth below said surface, wherein said conductive sub-surface regions form a sub-surface structure for routing a body-bias voltage, wherein said sub-surface structure has a perimeter;

an isolation structure formed within said perimeter of said sub-surface structure such that said isolation structure creates a gap in said sub-surface structure; and

at least one metal structure formed above said surface, wherein said metal structure spans said gap and is coupled to said sub-surface structure via a plurality of tap contacts.

2. The semiconductor device as recited in claim 1 wherein said sub-surface structure is a diagonal sub-surface mesh structure.

3. The semiconductor device as recited in claim 1 wherein each conductive sub-surface region has an N-type doping.

4. The semiconductor device as recited in claim 1 wherein each conductive sub-surface region has a P-type doping.

5. The semiconductor device as recited in claim 1 wherein each conductive sub-surface region has a strip shape.

6. The semiconductor device as recited in claim 1 wherein said metal structure has a metal wire shape.

7. The semiconductor device as recited in claim 1 further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said metal structure that overlaps said sub-surface structure, wherein each second conductive sub-surface region has a continuous sub-surface layer shape.

8. A semiconductor device having a surface, comprising:

a first plurality of conductive sub-surface regions of a first conductivity each formed beneath a well comprising a channel of said semiconductor device and each buried at a depth below said surface, wherein said first plurality of conductive sub-surface regions form a first sub-surface structure for routing a body-bias voltage;

a second plurality of conductive sub-surface regions of said first conductivity each formed beneath said surface and each buried at a depth below said surface, wherein said second plurality of conductive sub-surface regions form a second sub-surface structure for routing said body-bias voltage;

an isolation structure formed between said first sub-surface structure and said second sub-surface structure such that said isolation structure creates a gap between said first sub-surface structure and said second sub-surface structure; and

at least one metal structure formed above said surface, wherein said metal structure spans said gap and is coupled to said first sub-surface structure and said second sub-surface structure via a plurality of tap contacts.

9. The semiconductor device as recited in claim 8 wherein said first sub-surface structure is a first diagonal sub-surface mesh structure, and wherein said second sub-surface structure is a second diagonal sub-surface mesh structure.

10. The semiconductor device as recited in claim 8 wherein each conductive sub-surface region has an N-type doping.

11. The semiconductor device as recited in claim 8 wherein each conductive sub-surface region has a P-type doping.

12. The semiconductor device as recited in claim 8 wherein each conductive sub-surface region has a strip shape.

13. The semiconductor device as recited in claim 8 wherein said metal structure has a metal wire shape.

14. The semiconductor device as recited in claim 8 further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said metal structure that overlaps said first and second sub-surface structures, wherein each second conductive sub-surface region has a continuous sub-surface layer shape.

15. A semiconductor device having a surface, comprising:

a plurality of conductive sub-surface regions of a first conductivity each formed beneath a well comprising a channel of said semiconductor device and each buried at a depth below said surface, wherein said conductive sub-surface regions form a sub-surface structure for routing a body-bias voltage, wherein said sub-surface structure has a perimeter;

an isolation structure formed within said perimeter of said sub-surface structure such that said isolation structure creates a gap in said sub-surface structure; and

at least one structure that spans said gap and is coupled to said sub-surface structure.

16. The semiconductor device as recited in claim 15 wherein said sub-surface structure is a diagonal sub-surface mesh structure.

17. The semiconductor device as recited in claim 15 wherein each conductive sub-surface region has an N-type doping.

18. The semiconductor device as recited in claim 15 wherein each conductive sub-surface region has a P-type doping.

19. The semiconductor device as recited in claim 15 wherein each conductive sub-surface region has a strip shape.

20. The semiconductor device as recited in claim 15 wherein said structure is a polysilicon wire.

21. The semiconductor device as recited in claim 15 wherein said structure is a diffusion wire.

22. The semiconductor device as recited in claim 15 wherein said structure is a silicide wire.

23. The semiconductor device as recited in claim 15 further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said structure that overlaps said sub-surface structure, wherein each second conductive sub-surface region has a continuous sub-surface layer shape.

24. The semiconductor device as recited in claim 15 wherein said isolation structure divides said sub-surface structure into a first portion and a second portion.

25. The semiconductor device as recited in claim 1 , wherein a pattern of said plurality of conductive sub-surface regions is selected based on resistance characteristics of a conductive path for routing said body-bias voltage.

26. The semiconductor device as recited in claim 25 , wherein said pattern is selected to prevent isolation of wells of said semiconductor device.

27. The semiconductor device as recited in claim 1 , wherein a pattern, location and size of said plurality of conductive sub-surface regions is selected based on the distribution of wells of said semiconductor device.

28. The semiconductor device as recited in claim 1 , wherein said isolation structure creates a gap that separates said conductive sub-surface regions to at least two regions.

29. The semiconductor device as recited in claim 1 , wherein said isolation structure creates a gap that interrupts said conductive sub-surface regions.

30. The semiconductor device as recited in claim 8 , wherein a pattern of said first and said second plurality of conductive sub-surface regions are selected based on resistance characteristics of a conductive path for routing said body-bias voltage.

31. The semiconductor device as recited in claim 30 , wherein said pattern is selected to prevent isolation of wells of said semiconductor device.

32. The semiconductor device as recited in claim 8 , wherein a pattern, location and size of said plurality of conductive sub-surface regions is selected based on the distribution of wells of said semiconductor device.

33. The semiconductor device as recited in claim 8 , wherein said isolation structure creates a gap that separates said conductive sub-surface regions to at least two regions.

34. The semiconductor device as recited in claim 8 , wherein said isolation structure creates a gap that interrupts said conductive sub-surface regions.

35. The semiconductor device as recited in claim 15 , wherein a pattern of said plurality of conductive sub-surface regions is selected based on resistance characteristics of a conductive path for routing said body-bias voltage.

36. The semiconductor device as recited in claim 35 , wherein said pattern is selected to prevent isolation of wells of said semiconductor device.

37. The semiconductor device as recited in claim 15 , wherein a pattern, location and size of said plurality of conductive sub-surface regions is selected based on the distribution of wells of said semiconductor device.

38. The semiconductor device as recited in claim 15 , wherein said isolation structure creates a gap that separates said conductive sub-surface regions to at least two regions.

39. The semiconductor device as recited in claim 15 , wherein said isolation structure creates a gap that interrupts said conductive sub-surface regions.