Patent Assignment
Reel/Frame 022454/0522
Merger
Recorded: 2009-03-26
Received: 2009-03-26
Pages: 13
Assignor
TRANSMETA CORPORATION
Executed: 2009-01-27
Assignee
TRANSMETA LLC
C/O NOVAFORA, INC., 2460 NORTH FIRST STREET, SUITE 200, SAN JOSE, CA, 95131, UNITED STATES
Covered Properties
(100)
Systems and Methods for Control of Integrated Circuits Comprising Body Biasing Systems
Application:
12/410,249 →
Power Efficient Multiplexer
Application:
12/397,085 →
Secure Memory Access System and Method
Application:
12/391,998 →
Method and System for Automated Schematic Diagram Conversion to Support Semiconductor Body Bias Designs
Application:
12/392,022 →
Triple Latch Flip Flop System and Method
Application:
12/391,993 →
Processing Bypass Directory Trancking System and Method
Application:
12/353,064 →
Apparatus for Controlling Semiconductor Chip Characteristics
Application:
12/346,633 →
Controlling Temperature in a Semiconductor Device
Application:
12/330,324 →
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Application:
12/277,227 →
Explicit Control of Speculation
Application:
12/268,304 →
Method and System for Using External Storage to Amortize Cpu Cycle Utilization
Application:
12/259,262 →
Dynamic Ring Oscillators
Application:
12/194,504 →
Advanced Repeater with Duty Cycle Adjustment
Application:
12/181,221 →
Checking for Instruction Invariance to Execute Previously Obtained Translation Code by Comparing Instruction to a Copy Stored When Write Operation to the Memory Portion Occur
Application:
12/177,836 →
Column Select Multiplexer Circuit for a Domino Random Access Memory Array
Application:
12/165,432 →
Structure for Spanning Gap in Body-Bias Voltage Routing Structure
Application:
12/140,197 →
Restoring Processor Context in Response to Processor Power-Up
Application:
12/136,679 →
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Application:
12/127,648 →
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Application:
12/127,768 →
Advanced Repeater Utilizing Signal Distribution Delay
Application:
12/124,136 →
Memory Management for Cache Consistency
Application:
12/121,531 →
Servo Loop for Well Bias Voltage Source
Application:
12/107,733 →
Pipeline Replay Support for Multicycle Operations
Application:
12/042,224 →
Closed Loop Feedback Control of Integrated Circuits
Application:
12/037,784 →
Checking for Exception by Floating Point Instruction Reordered Across Branch by Comparing Current Status in Fp Status Register Against Last Status Copied in Shadow Register
Application:
12/037,872 →
Method for Increasing the Speed of Speculative Execution
Application:
12/037,853 →
Stacked Inverter Delay Chain
Application:
12/037,884 →
Method and System for Protecting Processors from Unauthorized Debug Access
Application:
12/033,864 →
Software Controlled Transistor Body Bias
Application:
12/033,832 →
Leakage Efficient Anti-Glitch Filter
Application:
12/033,712 →
Selective Coupling of Voltage Feeds for Body Bias Voltage in an Integrated Circuit Device
Application:
12/033,840 →
Method and Apparatus for Improving Segmented Memory Addressing
Application:
12/033,784 →
Voltage Compensated Integrated Circuits
Application:
12/030,180 →
Supporting Multiple Byte Order Formats in a Computer System
Application:
12/030,149 →
Selective coupling of voltage feeds for body bias voltage in an integrated circuit device
Application:
12/069,670 →
Sub-Surface Region with Diagonal Gap Regions
Application:
12/011,665 →
System and Method for Measuring Negative Bias Thermal Instability with a Ring Oscillator
Application:
12/006,473 →
A Method and System for a Tiling Bias Design to Facilitate Efficient Design Rule Checking
Application:
12/005,018 →
Setting a Flag Bit to Defer Event Handling to a Safe Point in an Instruction Stream
Application:
12/002,983 →
Configurable Delay Chain with Stacked Inverter Delay Elements
Application:
12/002,988 →
Using Standard Pattern Tiles and Custom Pattern Tiles to Generate a Semiconductor Design Layout Having a Deep Well Structure for Routing Body-Bias Voltage
Application:
11/999,279 →
Repeater Circuit with High Performance Repeater Mode and Normal Repeater Mode, Wherein High Performance Repeater Mode Has Fast Reset Capability
Application:
11/999,293 →
Ring Based Impedance Control of an Output Driver
Application:
11/986,337 →
Transitioning to and from a Sleep State of a Processor
Application:
11/894,991 →
Elastic Pipeline Latch with a Safe Mode
Application:
11/893,221 →
System and Method for Reducing Temperature Variation During Burn In
Application:
11/881,006 →
Systems and Methods for Integrated Circuits Comprising Multiple Body Bias Domains
Application:
11/880,351 →
System and Method for Reducing Heat Dissipation During Burn-In
Application:
11/827,290 →
Adaptive Power Control Based on Pre Package Characterization of Integrated Circuits
Application:
11/810,516 →
Supporting Speculative Modification in a Data Cache
Application:
11/807,629 →
Diagonal Deep Well Region for Routing Body-Bias Voltage for Mosfets in Surface Well Regions
Application:
11/799,496 →
Systems and Methods for Adjusting Threshold Voltage
Application:
11/787,908 →
History Based Pipelined Branch Prediction
Application:
11/786,336 →
Repeater Circuit Having Different Operating and Reset Voltage Ranges, and Methods Thereof
Application:
11/703,323 →
Method and Apparatus for Optimizing Body Bias Connections in Cmos Circuits Using a Deep N-Well Grid Structure
Application:
11/649,443 →
System Management Mode Code Modifications to Increase Computer System Security
Application:
11/644,224 →
System and Method for Characterizing a Potential Distribution
Application:
11/642,187 →
Systems and Methods for Determining Device Temperature
Application:
11/639,603 →
Method and System for Conservatively Managing Store Capacity Available to a Processor Issuing Stores
Application:
11/638,236 →
Pipeline Replay Support for Unaligned Memory Operations
Application:
11/594,672 →
Servo Loop for Well Bias Voltage Source
Application:
11/591,431 →
Braided Set Associative Caching Techniques
Application:
11/583,463 →
Dynamic Chip Control
Application:
11/529,865 →
Signal Generator with Output Frequency Greater Than the Oscillator Frequency
Application:
11/540,387 →
Processing Bypass Directory Tracking System and Method
Application:
11/540,789 →
Processing Bypass Register File System and Method
Application:
11/540,766 →
Methods and Systems for Dynamically Changing Device Operating Conditions
Application:
11/540,117 →
Raised Source/Drain with Super Steep Retrograde Channel
Application:
11/529,972 →
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Application:
11/528,031 →
System for on-Chip Temperature Measurement in Integrated Circuits
Application:
11/524,526 →
A Method and System for Storing and Retrieving a Translation of Target Program Instruction from a Host Processor Using Fast Look-Up of Indirect Branch Destination in a Dynamic Translation System
Application:
11/524,044 →
Frequency Specific Closed Loop Feedback Control of Integrated Circuits
Application:
11/512,900 →
Switching to Original Code Comparison of Modifiable Code for Translated Code Validity When Frequency of Detecting Memory Overwrites Exceeds Threshold
Application:
11/507,779 →
Method and System for Providing Hardware Support for Memory Protection and Virtual Memory Address Translation for a Virtual Machine
Application:
11/500,575 →
Closed Loop Feedback Control of Integrated Circuits
Application:
11/490,356 →
Enhanced Clock Signal Flexible Distribution System and Method
Application:
11/479,616 →
Cross Point Switch
Application:
11/479,618 →
Triple Latch Flip Flop System and Method
Application:
11/480,107 →
Dual Ported Replicated Data Cache
Application:
11/479,630 →
Modifications to increase computer system security
Application:
11/479,703 →
Processor modifications to increase computer system security
Application:
11/479,486 →
Double Diamond Clock and Power Distribution
Application:
11/477,970 →
Circuits and Methods for Detecting and Assisting Wire Transitions
Application:
11/473,608 →
Method and System for Caching Attribute Data for Matching Attributes with Physical Addresses
Application:
11/454,355 →
System and Method for Identifying Tlb Entries Associated with a Physical Address of a Specified Range
Application:
11/449,950 →
Layout Pattern for Deep Well Region to Facilitate Routing Body-Bias Voltage
Application:
11/449,952 →
System and Method for Handling Direct Memory Accesses
Application:
11/439,361 →
Inverting Zipper Repeater Circuit
Application:
11/435,692 →
Adaptive Power Control
Application:
11/411,309 →
Systems and Methods for Reordering Processor Instructions
Application:
11/400,631 →
Systems and Methods for Integrated Circuits Comprising Multiple Body Biasing Domains
Application:
11/400,368 →
Multi-portioned instruction memory
Application:
11/395,627 →
Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
Application:
11/394,521 →
Multi-Write Memory Circuit with a Data Input and a Clock Input
Application:
11/395,017 →
Multi-Write Memory Circuit with Multiple Data Inputs
Application:
11/396,114 →
Techniques for Detecting and Correcting Errors in a Memory Device
Application:
11/395,710 →
Conversion of an Soi Design Layout to a Bulk Design Layout
Application:
11/393,555 →
Stabilization Component for a Substrate Potential Regulation Circuit
Application:
11/358,482 →
Circuits, Systems and Methods Relating to a Dynamic Dual Domino Ring Oscillator
Application:
11/322,896 →
Circuits, Systems and Methods Relating to Dynamic Ring Oscillators
Application:
11/322,595 →