Conversion of an SOI design layout to a bulk design layout
View Patent ↗An SOI design layout is converted to a bulk design layout. According to a method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, an insulator layer of the SOI process beneath active devices in the first semiconductor design layout is removed. A conductive sub-surface structure for routing voltage is added to the first semiconductor design layout. Further, the active devices from the SOI process are converted to the bulk process to form the second semiconductor design layout without requiring a relayout of the first semiconductor design layout on a semiconductor surface. The bulk design layout is utilized to fabricate a semiconductor device having a plurality of active devices.
1. A method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, said method comprising:
removing an insulator layer of said SOI process beneath active devices in said first semiconductor design layout;
adding to said first semiconductor design layout a conductive sub-surface structure for routing voltage; and
converting said active devices from said SOI process to said bulk process to form said second semiconductor design layout without requiring a relayout of said first semiconductor design layout on a semiconductor surface.
2. The method as recited in claim 1 wherein said conductive sub-surface structure is utilized to route a supply voltage to a portion of said active devices.
3. The method as recited in claim 1 wherein said conductive sub-surface structure is utilized to route a body voltage for biasing to a portion of said active devices.
4. The method as recited in claim 1 further comprising:
adding to said first semiconductor design layout a second conductive sub-surface structure for routing voltage, wherein said conductive sub-surface structure is utilized to route a first supply voltage to a first portion of said active devices, and wherein said second conductive sub-surface structure is utilized to route a second supply voltage to a second portion of said active devices.
5. The method as recited in claim 4 further comprising:
isolating said conductive sub-surface structure from said second conductive sub-surface structure.
6. The method as recited in claim 1 further comprising:
adding to said first semiconductor design layout a second conductive sub-surface structure for routing voltage, wherein said conductive sub-surface structure is utilized to route a first body voltage for biasing to a first portion of said active devices, and wherein said second conductive sub-surface structure is utilized to route a second body voltage for biasing to a second portion of said active devices.
7. The method as recited in claim 6 further comprising:
isolating said conductive sub-surface structure from said second conductive sub-surface structure.
8. The method as recited in claim 1 further comprising:
classifying said active devices into a first group and into a second group, wherein said first group represents active devices having a surface N-well with sufficient area for at least one tap thereto, and wherein said second group represents active devices having a surface N-well with insufficient area for at least one tap thereto, and
wherein said adding to said first semiconductor design layout said conductive sub-surface structure for routing voltage comprises:
placing said conductive sub-surface structure between at least one active device from said first group and at least one active device from said second group.
9. The method as recited in claim 1 wherein said conductive sub-surface structure comprises a deep N-well mesh.
10. The method as recited in claim 1 wherein said conductive sub-surface structure comprises:
a substrate having a first type of doping;
an epitaxial layer having a second type of doping and disposed above said substrate; and
a via connection disposed through said epitaxial layer to connect said substrate to a surface well, wherein said via connection and said surface well have said first type of doping.
11. The method as recited in claim 10 wherein said first type of doping is an N-type doping and wherein said second type of doping is a P-type doping.
12. The method as recited in claim 1 wherein said conductive sub-surface structure comprises:
a substrate having a first type of doping;
a first epitaxial layer having a second type of doping and disposed above said substrate;
a second epitaxial layer having said first type of doping and disposed above said first epitaxial layer;
a first via connection disposed through said first epitaxial layer to connect said substrate to said second epitaxial layer, wherein said first via connection has said first type of doping; and
a second via connection disposed through said second epitaxial layer to connect said first epitaxial layer to a surface well, wherein said second via connection and said surface well have said second type of doping.
13. The method as recited in claim 12 wherein said first type of doping is a P-type doping and wherein said second type of doping is an N-type doping.
14. A computer-readable medium comprising computer-executable instructions stored therein for performing a method of converting a first semiconductor design layout based on an Silicon-on-Insulator (SOI) process to a second semiconductor design layout based on a bulk process, said method comprising:
removing an insulator layer of said SOI process beneath active devices in said first semiconductor design layout;
adding to said first semiconductor design layout a conductive sub-surface structure for routing voltage; and
converting said active devices from said SOI process to said bulk process to form said second semiconductor design layout without requiring a relayout of said first semiconductor design layout on a semiconductor surface.
15. The computer-readable medium as recited in claim 14 wherein said conductive sub-surface structure is utilized to route a supply voltage to a portion of said active devices.
16. The computer-readable medium as recited in claim 14 wherein said conductive sub-surface structure is utilized to route a body voltage for biasing to a portion of said active devices.
17. The computer-readable medium as recited in claim 14 wherein said method further comprises:
adding to said first semiconductor design layout a second conductive sub-surface structure for routing voltage, wherein said conductive sub-surface structure is utilized to route a first supply voltage to a first portion of said active devices, and wherein said second conductive sub-surface structure is utilized to route a second supply voltage to a second portion of said active devices.
18. The computer-readable medium as recited in claim 17 wherein said method further comprises:
isolating said conductive sub-surface structure from said second conductive sub-surface structure.
19. The computer-readable medium as recited in claim 14 wherein said method further comprises:
adding to said first semiconductor design layout a second conductive sub-surface structure for routing voltage, wherein said conductive sub-surface structure is utilized to route a first body voltage for biasing to a first portion of said active devices, and wherein said second conductive sub-surface structure is utilized to route a second body voltage for biasing to a second portion of said active devices.
20. The computer-readable medium as recited in claim 19 wherein said method further comprises:
isolating said conductive sub-surface structure from said second conductive sub-surface structure.
21. The computer-readable medium as recited in claim 14 wherein said method further comprises:
classifying said active devices into a first group and into a second group, wherein said first group represents active devices having a surface N-well with sufficient area for at least one tap thereto, and wherein said second group represents active devices having a surface N-well with insufficient area for at least one tap thereto, and
wherein said adding to said first semiconductor design layout said conductive sub-surface structure for routing voltage comprises:
placing said conductive sub-surface structure between at least one active device from said first group and at least one active device from said second group.
22. The computer-readable medium as recited in claim 14 wherein said conductive sub-surface structure comprises a deep N-well mesh.
23. The computer-readable medium as recited in claim 14 wherein said conductive sub-surface structure comprises:
a substrate having a first type of doping;
an epitaxial layer having a second type of doping and disposed above said substrate; and
a via connection disposed through said epitaxial layer to connect said substrate to a surface well, wherein said via connection and said surface well have said first type of doping.
24. The computer-readable medium as recited in claim 23 wherein said first type of doping is an N-type doping and wherein said second type of doping is a P-type doping.
25. The computer-readable medium as recited in claim 14 wherein said conductive sub-surface structure comprises:
a substrate having a first type of doping;
a first epitaxial layer having a second type of doping and disposed above said substrate;
a second epitaxial layer having said first type of doping and disposed above said first epitaxial layer;
a first via connection disposed through said first epitaxial layer to connect said substrate to said second epitaxial layer, wherein said first via connection has said first type of doping; and
a second via connection disposed through said second epitaxial layer to connect said first epitaxial layer to a surface well, wherein said second via connection and said surface well have said second type of doping.
26. The computer-readable medium as recited in claim 25 wherein said first type of doping is a P-type doping and wherein said second type of doping is an N-type doping.