Triple latch flip flop system and method
View Patent ↗A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.
1. A triple latch flip-flop system comprising:
a pull up latch for driving a pull up node, pull up latch comprises a priority on set operation;
a pull down latch for driving a pull down node;
a primary latch for recording a state; and
an output derived from the outputs of said pull up latch, pull down latch and said primary latch.
2. A triple latch flip flop system of claim 1 wherein said pull up latch, pull down latch and primary latch comprise static logic gates.
3. A triple latch flip flop system of claim 1 wherein said pull down latch comprises a priority on reset operation.
4. A triple latch flip flop system of claim 1 wherein said pull up latch, pull down latch and primary latch comprise dynamic gates.
5. A triple latch flip flop system of claim 4 wherein said pull down latch comprises a priority on reset operation.
6. A triple latch flip-flop method comprising:
precharging a triple latch flip flop system, wherein said evaluating includes releasing a state hold on a pull-up latch and pull-down latch;
evaluating data through said triple latch flip flop system;
blocking data in said triple latch flip flop system; and
returning said triple latch flip flop system to a pre-charge state.
7. A triple latch flip-flop method of claim 6 wherein said precharging includes shutting off output drivers and putting a primary latch into a retention mode.
8. A triple latch flip-flop method of claim 6 wherein said precharging wherein said precharging includes forcing a pull-up latch into a set state and a pull-down latch into a reset state.
9. A triple latch flip-flop method of claim 6 wherein said precharging weakly drives an output.
10. A triple latch flip-flop method of claim 6 wherein said precharging includes holding a output state until a clock trigger.
11. A triple latch flip-flop method of claim 6 wherein said evaluating includes clocking said triple latch flip flop system.
12. A triple latch flip-flop method of claim 6 wherein said evaluating includes resetting a pull up latch.
13. A triple latch flip-flop method of claim 6 wherein said evaluating includes setting a pull down latch.
14. A triple latch flip-flop method of claim 6 wherein said evaluating comprise resetting a pull up latch and strongly driving an output node;
setting a primary latch; and
instructing a pull down latch to reset.
15. A triple latch flip-flop method of claim 6 further comprising performing race margin correction.