Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
View Patent ↗Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
1. A method of routing a body-bias voltage to surface wells of a first conductivity in a semiconductor device, said method comprising:
forming a sub-surface layer of said first conductivity below a surface of said semiconductor device and below said surface wells;
forming gap regions in said sub-surface layer, wherein said gap regions are oriented diagonally with respect to an orientation of said surface wells;
electrically coupling said sub-surface layer to said surface wells to create a conductive path; and
applying said body-bias voltage to said sub-surface layer.
2. The method as recited in claim 1 wherein said sub-surface layer has an N-type doping.
3. The method as recited in claim 2 wherein said surface wells have an N-type doping.
4. The method as recited in claim 3 wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
5. The method as recited in claim 1 wherein said sub-surface layer has a P-type doping.
6. The method as recited in claim 5 wherein said surface wells have a P-type doping.
7. The method as recited in claim 6 wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).
8. A method of routing a body-bias voltage to surface wells of a first conductivity in a semiconductor device, said method comprising:
forming a sub-surface layer of said first conductivity below a surface of said semiconductor device and below said surface wells,
forming diagonally-oriented gap regions in said sub-surface layer, wherein said diagonally-oriented gap regions are oriented diagonally with respect to an orientation of said surface wells;
electrically coupling said sub-surface layer to said surface wells to create a conductive path; and
applying said body-bias voltage to said sub-surface layer.
9. The method as recited in claim 8 wherein said sub-surface layer has an N-type doping.
10. The method as recited in claim 9 wherein said surface wells have an N-type doping.
11. The method as recited in claim 10 wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
12. The method as recited in claim 8 wherein said sub-surface layer has a P-type doping.
13. The method as recited in claim 12 wherein said surface wells have a P-type doping.
14. The method as recited in claim 13 wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).
15. A method of routing a body-bias voltage to first surface wells of a first conductivity in a semiconductor device, said method comprising:
forming a sub-surface layer of said first conductivity below a surface of said semiconductor device, below said first surface wells, and below second surface wells of a second conductivity
forming gap regions in said sub-surface layer, wherein said gap regions are oriented diagonally with respect to an orientation of said first surface wells without isolating said second surface wells;
electrically coupling said sub-surface layer to said surface wells to create a conductive path; and
applying said body-bias voltage to said sub-surface layer.
16. The method as recited in claim 15 wherein said sub-surface layer has an N-type doping.
17. The method as recited in claim 16 wherein said first surface wells have an N-type doping and wherein said second surface wells have a P-type doping.
18. The method as recited in claim 17 wherein each first surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
19. The method as recited in claim 15 wherein said sub-surface layer has a P-type doping.
20. The method as recited in claim 19 wherein said first surface wells have a P-type doping, wherein said second surface wells have an N-type doping, and wherein each first surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).