Secure memory access system and method
View Patent ↗A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented.
1. A method comprising:
storing memory configuration information; and
in response to switching from a first processor operating mode to a second processor operating mode, performing a security enhancing operation on the memory configuration information.
2. The method of claim 1 , wherein said storing comprises:
receiving the memory configuration information at memory type range registers (MTRRs).
3. The method of claim 1 , wherein said storing comprises:
receiving the memory configuration information at a programmable attribute table (PAT).
4. The method of claim 1 , wherein said performing comprises:
moving the memory configuration information from a first memory location to a second memory location.
5. The method of claim 4 , wherein said performing further comprises:
changing the memory configuration information at the first memory location.
6. The method of claim 4 further comprising:
in response to switching from the second processor operating mode to the first processor operating mode, performing a second security enhancing operation on the memory configuration information.
7. The method of claim 6 , wherein said performing the second security enhancing operation comprises:
moving the memory configuration information from the second memory location to the first memory location.
8. The method of claim 1 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.
9. A method comprising:
storing memory configuration information associated with a processor operating mode in a first memory location; and
in response to switching into the processor operating mode, performing a security enhancing operation on the memory configuration information by using the first memory location and a second memory location.
10. The method of claim 9 , wherein said storing comprises:
receiving the memory configuration information at the first memory location in memory type range registers (MTRRs).
11. The method of claim 9 , wherein said storing comprises:
receiving the memory configuration information at the first memory location in a programmable attribute table (PAT).
12. The method of claim 9 , wherein said performing comprises:
moving the memory configuration information from the first memory location to the second memory location.
13. The method of claim 12 , wherein said performing further comprises:
changing the memory configuration information at the first memory location.
14. The method of claim 12 further comprising:
in response to switching out of the processor operating mode, performing a second security enhancing operation on the memory configuration information.
15. The method of claim 14 , wherein said performing the second security enhancing operation comprises:
moving the memory configuration information from the second memory location to the first memory location.
16. The method of claim 9 , wherein the processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.
17. A method comprising:
detecting a mode-triggering event;
if the mode triggering event is detected, switching from a first processor operating mode to a second processor operating mode; and
performing a security enhancing operation on memory configuration information associated with the second processor operating mode.
18. The method of claim 17 , wherein said performing comprises:
moving the memory configuration information from a first memory location to a second memory location.
19. The method of claim 18 , wherein said performing further comprises:
changing the memory configuration information at the first memory location.
20. The method of claim 18 further comprising:
in response to switching from the second processor operating mode to the first processor operating mode, performing a second security enhancing operation on the memory configuration information.
21. The method of claim 20 , wherein said performing the second security enhancing operation comprises:
moving the memory configuration information from the second memory location to the first memory location.
22. The method of claim 17 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.