Multi-write memory circuit with a data input and a clock input
View Patent ↗Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.
1. A memory circuit comprising:
a state-storage feedback loop having a clock input and a data input, wherein the memory circuit is configured to concurrently introduce a same data input value into the state-storage feedback loop at multiple points on the state-storage feedback loop, wherein the multiple points correspond to the input sides of selected circuit elements in the state-storage feedback loop.
2. The memory circuit of claim 1 , wherein the state-storage feedback loop comprises an even number of circuit elements coupled in series, and wherein the multiple points correspond to points between every other circuit element.
3. The memory circuit of claim 2 , wherein each circuit element between the every other circuit element is configured to receive the clock input.
4. The memory circuit of claim 1 , wherein the state-storage feedback loop comprises a same number of inverters and three-state inverters, and wherein the inverters and the three-state inverters are coupled alternately in series and configured such that a first inverter drives a first three-state inverter that drives a second inverter that drives a second three-state inverter.
5. The memory circuit of claim 4 , wherein the multiple points correspond to inputs of the inverters.
6. The memory circuit of claim 4 , wherein each of the three-state inverters is configured to receive the clock input.
7. The memory circuit of claim 4 , wherein the state-storage feedback loop comprises at least two inverters and at least two three-state inverters.
8. The memory circuit of claim 1 , further comprising a plurality of three-state inverters, wherein a three-state inverter of the plurality of three-state inverters is coupled between the data input and each of the multiple points.
9. The memory circuit of claim 8 , wherein each of the three-state inverters comprises an inverter, a first p-type device, a second p-type device, a first n-type device, and a second n-type device.
10. A memory circuit comprising:
a clock input coupled to a state-storage feedback loop having a plurality of stages;
a data input coupled to the stages, wherein the memory circuit is configured such that:
the data input has a same state that is written into the stages; and
the same state at the data input is concurrently written into the stages on the input side of an element in a stage; and
an output coupled to the stages, wherein a first state at the data input and a second state at the data input that is subsequent to the first state are both configured to affect a state at the output.
11. The memory circuit of claim 10 , wherein the stages are coupled in series, wherein the stages comprise a stage having a first element and a second element coupled in series, wherein the state at the data input is configured to be input to the first element, and wherein the second element is configured to receive both the clock input and a state that is output from the first element.
12. The memory circuit of claim 10 , wherein the stages comprise a stage having an inverter and a three-state inverter coupled in series.
13. The memory circuit of claim 12 , wherein the state at the data input is configured to be input to the inverter in the stage.
14. The memory circuit of claim 12 , wherein the three-state inverter in the stage is configured to receive both the clock input and a state from the inverter in the stage.
15. The memory circuit of claim 12 , wherein for each of the stages, the three-state inverter comprises an inverter, a first p-type device, a second p-type device, a first n-type device, and a second n-type device.
16. The memory circuit of claim 10 , further comprising a plurality of three-state inverters, wherein a three-state inverter of the plurality of three-state inverters is coupled between the data input and the stages.
17. A method of writing state to a memory circuit, the method comprising:
receiving a clock input at a first plurality of points in a state-storage feedback loop of the memory circuit;
receiving a data input at a second plurality of points on the state-storage feedback loop, wherein the data input has a value associated therewith, and wherein a same value of the data input is concurrently sensed at each of the second plurality of points, wherein the points in the second plurality each correspond to the input side of a circuit element in the state-storage feedback loop; and
propagating the data input from the second plurality of points to other points in the state-storage feedback loop.
18. The method of claim 17 , further comprising receiving the data input at alternate circuit elements of the state-storage feedback loop.
19. The method of claim 18 , further comprising:
receiving the clock input at circuit elements between the alternate circuit elements; and
receiving, from the alternate circuit elements, a state at the circuit elements between the alternate circuit elements.
20. The method of claim 17 , wherein the state-storage feedback loop comprises a same number of inverters and three-state inverters, and wherein the inverters and the three-state inverters are coupled alternately in series and configured such that a first inverter drives a first three-state inverter that drives a second inverter that drives a second three-state inverter.
21. The method of claim 20 , further comprising receiving the data input at inputs of the inverters.
22. The method of claim 20 , further comprising receiving a state and a clock input at the three-state inverters.
23. The method of claim 20 , wherein the state-storage feedback loop comprises at least two inverters and at least two three-state inverters.
24. The method of claim 17 , wherein the memory circuit further comprises a plurality of three-state inverters, wherein a three-state inverter of the plurality of three-state inverters is coupled between a data input of the memory circuit and each point of the second plurality of points.
25. The method of claim 24 , wherein each of the three-state inverters comprises an inverter, a first p-type device, a second p-type device, a first n-type device, and a second n-type device.