Dynamic ring oscillators
View Patent ↗A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.
1. A circuit comprising:
a plurality of domino circuit chains coupled in series, wherein an output of each domino circuit chain is coupled to an input of another domino circuit chain and the output of each domino circuit chain clocks an earlier domino circuit chain, and wherein a trigger input of a first one of the plurality of domino circuit chains receives a trigger signal.
2. The circuit of claim 1 , wherein each domino circuit chain comprises:
an even number of domino circuits coupled in series, wherein the domino circuits of a given domino circuit chain are clocked substantially simultaneously.
3. The circuit of claim 2 , wherein the domino circuits comprise non-inverting domino circuits.
4. The circuit of claim 2 , wherein the domino circuits comprise N-footed domino circuits.
5. The circuit of claim 2 , wherein the domino circuits comprise P-footed domino circuits.
6. The circuit of claim 2 , wherein each domino circuit comprises:
a logic tree circuit including a first input coupled to a trigger input of the domino circuit and a second input coupled to a ring input of a given domino circuit;
a clocked pre-charge device coupled to the logic tree circuit and including an input coupled to a clock input of the given domino circuit;
a clocked cutoff device coupled to the logic tree circuit and including an input coupled to the clock input of the given domino circuit; and
an inverter including an input coupled to an output of the logic tree circuit and an output coupled to the ring output of the given domino circuit.
7. The circuit of claim 6 , wherein each domino circuit further comprises a latch circuit coupled between the output and the input of the inverter.
8. The circuit of claim 1 , further comprising a ring out inverter having an input coupled to the ring output of a second one of the plurality of domino circuit chains.
9. The circuit of claim 1 , further comprising a pulse generator coupled to the ring input of the first one of the plurality of domino circuit chains.
10. The circuit of claim 9 , wherein the pulse generator comprises:
an inhibit-to-evaluate margin delay circuit having an input coupled to an enable signal; and
a trigger-on-enable pulse generator circuit having an input coupled to the inhibit-to-evaluate margin delay circuit and an output coupled to the trigger input of the first one of the plurality of domino circuit chains.
11. The circuit of claim 9 , wherein the pulse generator is external to the plurality of domino circuit chains and does not arise from a component of the plurality of domino circuit chains.
12. The circuit of claim 1 , further comprising:
a plurality of clock buffer circuits, wherein an output of each clock buffer circuit is coupled to a given domino circuit chain; and
a plurality of inhibit and initialize gating circuits, wherein each inhibit and initialized gating circuit includes an output coupled to a given block buffer circuit, a first input coupled to an enable signal and a second input coupled the ring output of another domino circuit chain.
13. The circuit of claim 1 , wherein the trigger input of each of the domino circuit chains is disabled except for the first one of the plurality of domino circuit chains.
14. A circuit comprising:
a plurality of N-Footed domino circuit chains coupled in series, wherein a ring output of each N-Footed domino circuit chain is coupled to a ring input of another N-Footed domino circuit chain and the ring output of each N-Footed domino circuit chain clocks an earlier N-Footed domino circuit chain, and wherein a trigger input of a first one of the plurality of N-Footed domino circuit chains receives a trigger input;
a plurality of P-Footed domino circuit chains coupled in series, wherein a ring output of each P-Footed domino circuit chain is coupled to a ring input of another P-Footed domino circuit chain and the ring output of each P-Footed domino circuit chain clocks an earlier P-Footed domino circuit chain, and wherein a trigger input of a first one of the plurality of P-Footed domino circuit chains receives a trigger input;
a first frequency detector coupled to a ring output of a second one of the plurality of the plurality of N-footed domino circuit chains;
a second frequency detector coupled to a ring output of a second one of the plurality of the plurality of P-footed domino circuit chains; and
a frequency comparator circuit having a first input coupled to an output of the first frequency detector, a second input coupled to an output of the second frequency detector and outputting a frequency comparison signal.
15. The circuit of claim 14 , wherein:
the plurality of N-Footed domino circuit chains are self-untriggered; and
the plurality of P-Footed domino circuit chains are self-untriggered.
16. The circuit of claim 14 , wherein:
each N-Footed domino circuit chain comprises an even number of N-Footed non-inverting domino circuits coupled in series; and
each P-Footed domino circuit chain comprises the even number of P-Footed non-inverting domino circuits coupled in series.