IP Library Granted Patent US 8,650,555
Granted Patent B1
US 8,650,555 · App. 12/037,853 · Granted Feb 11, 2014

Method for increasing the speed of speculative execution

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Quick Facts
Patent No.
US 8,650,555
App. No.
12/037,853
Granted
Feb 11, 2014
Kind
B1
Abstract

A method of code execution by a processor including duplicating a first set of instructions to generate a second set of instructions, modifying the second set of instructions, executing the modified set of instructions, and upon exiting the modified set of instructions, loading an updated state of the processor.

Claims (40)

1. A method comprising:

storing a copy of a set of instructions in a memory accessible by a processor;

using the processor to modify the set of instructions to generate a modified set of instructions based on a selected trace, wherein said using the processor to modify includes changing branch instruction targets off the selected trace to a rollback instruction and the copy of the set of instructions;

speculatively executing the modified set of instructions in the processor; and

responsive to exiting the selected trace, halting said speculatively executing.

2. The method of claim 1 , wherein said using the processor to modify the set of instructions comprises modifying the set of instructions to increase execution efficiency thereof.

3. The method of claim 1 , wherein the set of instructions comprises a branch instruction, and wherein the modified set of instructions assumes the branch instruction will follow the selected trace.

4. The method of claim 1 , wherein said halting comprises:

in response to exiting the selected trace, executing the rollback instruction and the copy of the set of instructions.

5. The method of claim 1 , further comprising:

executing a commit instruction.

6. The method of claim 1 , further comprising:

detecting an asynchronous event that indicates a request to exit the selected trace.

7. The method of claim 6 , wherein the asynchronous event is at least one of an error, a mis-speculation, and an exception.

8. A method comprising:

storing a copy of a set of instructions in a memory accessible by a processor;

using the processor to modify the set of instructions to generate a modified set of instructions based on a selected trace, wherein said using the processor to modify includes changing branch instruction targets off the selected trace to a rollback instruction and the copy of the set of instructions;

speculatively executing the modified set of instructions in the processor;

responsive to exiting the selected trace, halting said speculatively executing the modified set of instructions; and

executing a commit instruction if exceptions are unraised.

9. The method of claim 8 , wherein said using the processor to modify the set of instructions comprises modifying the set of instructions to increase execution efficiency thereof.

10. The method of claim 8 , wherein the set of instructions comprises a branch instruction, and wherein the modified set of instructions assumes the branch instruction will follow the selected trace.

11. The method of claim 8 , wherein said halting comprises:

in response to exiting the selected trace, executing the rollback instruction and the copy of the set of instructions.

12. The method of claim 8 , further comprising:

detecting an asynchronous event that indicates a request to exit the selected trace.

13. The method of claim 12 , wherein the asynchronous event is at least one of an error, a mis-speculation, and an exception.

14. A method comprising:

storing a copy of a set of instructions in a memory accessible by a processor;

using the processor to modify the set of instructions to generate a modified set of instructions based on a selected trace, wherein said using the processor to modify includes changing branch instruction targets off the selected trace to a rollback instruction and the copy of the set of instructions;

speculatively executing the modified set of instructions in the processor; and

responsive to exiting the selected trace, halting said speculatively executing the modified set of instructions and executing the rollback instruction and the copy of the set of instructions.

15. The method of claim 14 , wherein said using the processor to modify the set of instructions comprises modifying the set of instructions to increase execution efficiency thereof.

16. The method of claim 14 , wherein the set of instructions comprises a branch instruction.

17. The method of claim 16 , wherein the modified set of instructions assumes the branch instruction will follow the selected trace.

18. The method of claim 14 , further comprising:

executing a commit instruction.

19. The method of claim 14 , further comprising:

detecting an asynchronous event that indicates a request to exit the selected trace.

20. The method of claim 19 , wherein the asynchronous event is at least one of an error, a mis-speculation, and an exception.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2020
From: INTELLECTUAL VENTURES ASSETS 154 LLC
To: LIBERTY PATENTS LLC
Reel/Frame 051632/0864 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2009
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 023268/0771 →
MERGER Recorded Mar 26, 2009
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 022454/0522 →