Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage
View Patent ↗A semiconductor design layout having a deep well structure for routing body-bias voltage is generated using standard pattern tiles and custom pattern tiles. These tiles have a tile shape and a tile size that fit an integer number of times into a grid unit of a grid for the semiconductor design layout.
1. A method of generating a semiconductor design layout, said method comprising:
placing a plurality of blocks of said semiconductor design layout on a grid having a grid unit that is larger than a minimum dimension available for said semiconductor design layout;
placing standard pattern tiles each standard pattern tile comprising a tile shape and a tile size such that said tile shape and said tile size fit an integer number of times into said grid unit; and
replacing, by a computer, any error-causing standard pattern tile with a custom pattern tile.
2. The method of claim 1 , wherein said replacing comprises:
performing design layout verification; and
if a design error is detected, identifying any standard pattern tile causing said design error.
3. The method of claim 2 , wherein said replacing further comprises:
selecting said custom pattern tile from a plurality of available custom pattern tiles; and
repeating performance of said design layout verification.
4. The method of claim 3 , wherein each available custom pattern tile comprises said tile shape and said tile size.
5. The method of claim 1 , wherein each standard pattern tile comprises a pattern dependent on arrangement of a conductive sub-surface structure for routing voltage.
6. The method of claim 5 , wherein said conductive sub-surface structure is arranged as at least one of a diagonal sub-surface mesh structure, a diagonal sub-surface strip structure, an axial sub-surface mesh structure, or an axial sub-surface strip structure.
7. The method of claim 5 , wherein said conductive sub-surface structure comprises an N-type doping.
8. The method of claim 5 , wherein said conductive sub-surface structure comprises a P-type doping.
9. A non-transitory computer-readable medium comprising computer-executable instructions stored therein, said computer-executable instructions comprising:
instructions to place a plurality of blocks of a semiconductor design layout on a grid having a grid unit that is larger than a minimum dimension available for said semiconductor design layout;
instructions to place standard pattern tiles, each standard pattern tile comprising a tile shape and a tile size such that said tile shape and said tile size fit an integer number of times into said grid unit; and
instructions to replace any error-causing standard pattern tile with a custom pattern tile.
10. The computer-readable medium of claim 9 , wherein said instructions to replace comprises:
instructions to perform design layout verification; and
instructions to identify any standard pattern tile causing a design error if said design error is detected.
11. The computer-readable medium of claim 10 , wherein said instructions to replace further comprises:
instructions to select said custom pattern tile from a plurality of available custom pattern tiles; and
instructions to repeat performance of said design layout verification.
12. The computer-readable medium of claim 11 , wherein each available custom pattern tile comprises said tile shape and said tile size.
13. The computer-readable medium of claim 9 , wherein each standard pattern tile comprises a pattern dependent on arrangement of a conductive sub-surface structure for routing voltage.
14. The computer-readable medium of claim 13 , wherein said conductive sub-surface structure is arranged as at least one of a diagonal sub-surface mesh structure, a diagonal sub-surface strip structure, an axial sub-surface mesh structure, or an axial sub-surface strip structure.
15. The computer-readable medium of claim 13 , wherein said conductive sub-surface structure comprises an N-type doping.
16. The computer-readable medium of claim 13 , wherein said conductive sub-surface structure comprises a P-type doping.
17. A method of generating a semiconductor design layout, said method comprising:
using a grid comprising a grid unit that is larger than a minimum dimension available for said semiconductor design layout;
placing standard pattern tiles each standard pattern tile comprising a tile shape and a tile size such that said tile shape and said tile size fit an integer number of times into said grid unit; and
replacing, by a computer, any error-causing standard pattern tile with a custom pattern tile.
18. The method of claim 17 , wherein said replacing comprises:
performing design layout verification; and
if a design error is detected, identifying any standard pattern tile causing said design error.
19. The method of claim 18 , wherein said replacing further comprises:
selecting said custom pattern tile from a plurality of available custom pattern tiles; and
repeating performance of said design layout verification.
20. The method of claim 19 , wherein each available custom pattern tile comprises said tile shape and said tile size.