Raised source/drain with super steep retrograde channel
View Patent ↗Systems and methods for raised source/drain with super steep retrograde channel. In accordance with a first embodiment of the present invention, in one embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments in accordance with the present invention may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
1. A semiconductor device comprising:
a substrate comprising a surface;
a gate oxide disposed above said surface comprising a gate oxide thickness; and
a super steep retrograde channel region formed at a depth below said surface, wherein said depth is about ten to thirty times said gate oxide thickness.
2. A semiconductor device of claim 1 wherein said substrate is disposed for accepting a body biasing voltage.
3. A semiconductor device of claim 1 further comprising a source structure disposed above said surface.
4. A semiconductor device of claim 3 wherein said source structure comprises epitaxially grown material.
5. A semiconductor device of claim 3 wherein said source structure comprises silicide.
6. A semiconductor device of claim 3 further comprising a source extension disposed beneath said source structure and wherein said source extension does not form a junction with said super steep retrograde channel region.
7. A semiconductor device of claim 1 wherein a horizontal extent of said super steep retrograde channel region is substantially limited to the horizontal extent of said gate oxide.
8. A semiconductor device comprising:
a substrate having a substrate thickness;
a source structure disposed above said substrate having a source thickness; and
wherein said substrate thickness is sufficient to accommodate said source thickness.
9. A semiconductor device of claim 8 wherein said substrate is disposed for applying a body biasing voltage.
10. A semiconductor device of claim 8 wherein said source structure comprises epitaxially grown material.
11. A semiconductor device of claim 8 wherein said source structure comprises silicide.
12. A semiconductor device of claim 8 further comprising a super steep retrograde channel region.
13. A semiconductor device of claim 12 —further comprising a source extension disposed in said substrate beneath said source structure.
14. A semiconductor device of claim 13 further comprising a lightly doped halo implant adjacent to said source extension.
15. A semiconductor device comprising:
a super steep retrograde channel region having a substantially linear body biasing voltage to threshold voltage characteristic; and
a raised source structure.
16. A semiconductor device of claim 15 wherein a body biasing voltage is coupled to said super steep retrograde channel region.
17. A semiconductor device of claim 15 further comprising:
a substrate comprising a surface;
a gate oxide disposed above said surface comprising a gate oxide thickness; and
wherein a depth of said super steep retrograde channel region below said surface is substantially within the range of ten to thirty times said gate oxide thickness.
18. A semiconductor device of claim 17 wherein a horizontal extent of said super steep retrograde channel region is substantially limited to the horizontal extent of said gate oxide.
19. A semiconductor device of claim 15 wherein a one unit change in applied body biasing voltage produces a change in threshold voltage substantially within the range of one tenth to one third of said unit.