Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
View Patent ↗A method for tagging cache entries to support context switching for virtual machines and for operating systems. The method includes, storing a plurality of entries within a cache of a CPU of a computer system, wherein each of the entries includes a context ID, handling a first portion of the entries as local entries when the respective context IDs indicate a local status, and handling a second portion of the entries as global entries when the respective context IDs indicate a global status.
1. A method comprising:
storing a selecting value, a first context ID, and a second context ID in at least one cache entry of cache entries in a virtually tagged cache;
storing a virtual address tag in the cache entries; and
searching the virtually tagged cache, wherein said searching comprises:
comparing a first context ID of a cache entry with a first provided context ID and generating a first match signal;
comparing a second context ID of the cache entry with a second provided context ID and generating a second match signal;
selecting a match signal from the first match signal and the second match signal based on the selecting value of the cache entry;
comparing the virtual address tag of the cache entry with a provided virtual address tag; and
generating a third match signal.
2. The method of claim 1 , wherein said searching further comprises:
performing a logical operation with the match signal, the third match signal, and a valid bit of the cache entry; and
generating an output match signal.
3. A method comprising:
storing a first context ID and a second context ID in at least one cache entry of cache entries in a virtually tagged cache;
storing a virtual address tag in the cache entries; and
searching the virtually tagged cache, wherein said searching comprises:
comparing a first context ID of a cache entry with a first provided context ID and generating a first match signal;
comparing a second context ID of the cache entry with a second provided context ID and generating a second match signal;
setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match;
comparing the virtual address tag of the cache entry with a provided virtual address tag; and
generating a third match signal.
4. The method of claim 3 , wherein said searching further comprises:
performing a logical operation with the match signal, the third match signal, and a valid bit of the cache entry; and
generating an output match signal.
5. A method comprising:
storing a first context ID and a second context ID in at least one entry of entries in a translation lookaside buffer (TLB);
storing a virtual address tag in the entries; and
searching the TLB, wherein said searching comprises:
comparing a first context ID of an entry with a first provided context ID and generating a first match signal;
comparing a second context ID of the entry with a second provided context ID and generating a second match signal;
setting a match signal to a match state if at least one of the first match signal or the second match signal indicates a match;
comparing the virtual address tag of the entry with a provided virtual address tag; and
generating a third match signal.
6. The method of claim 5 , wherein said searching further comprises:
using a signal to select the first provided context ID and the second provided context ID from a plurality of context ID registers.
7. The method of claim 6 , wherein at least one of the plurality of context ID registers stores a data context.
8. The method of claim 6 , wherein at least one of the plurality of context ID registers stores a code context.
9. The method of claim 5 , wherein said searching further comprises:
performing a logical operation with the match signal, the third match signal, and a valid bit of the entry; and
generating an output match signal.
10. A circuit comprising:
a first comparator operable to compare a first context ID of a cache entry with a first provided context ID and operable to output a first match signal;
a second comparator operable to compare a second context ID of the cache entry with a second provided context ID and operable to output a second match signal;
a third comparator operable to compare a virtual address tag of the cache entry with a provided virtual address tag and operable to output a third match signal;
a multiplexer operable to receive the first and second match signals and operable to output a match signal dependent on a selecting value of the cache entry; and
an AND gate operable to receive the match signal, the third match signal, and a valid bit of the cache entry and operable to generate an output match signal.
11. A circuit comprising:
a first comparator configured to compare a first context ID of a cache entry with a first provided context ID and configured to output a first match signal;
a second comparator configured to compare a second context ID of the cache entry with a second provided context ID and configured to output a second match signal;
an OR gate configured to receive the first and second match signals and configured to output a match signal;
a first multiplexer configured to receive outputs from a first plurality of registers and configured to output the first provided context ID in response to a signal; and
a second multiplexer configured to receive outputs from a second plurality of registers and configured to output the second provided context ID in response the signal.
12. The circuit of claim 11 further comprising:
a third comparator configured to compare a virtual address tag of the cache entry with a provided virtual address tag and configured to output a third match signal.
13. The circuit of claim 12 further comprising:
an AND gate configured to receive the match signal, the third match signal, and a valid bit of the cache entry and configured to generate an output match signal.