Selective coupling of voltage feeds for body bias voltage in an integrated circuit device
View Patent ↗An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.
1. An integrated circuit comprising:
a body bias distribution circuit operable to receive an externally applied voltage;
an internal voltage bus; and
a circuit component operable to couple said internal voltage bus to said distribution circuit absent said externally applied voltage.
2. An integrated circuit as described in claim 1 wherein said externally applied voltage is substantially applied to said distribution circuit when said externally applied voltage is applied.
3. An integrated circuit as described in claim 2 wherein said circuit component is a resistor element.
4. An integrated circuit as described in claim 2 further comprising an external pin coupled to said pad, said external pin for coupling with said externally supplied voltage.
5. An integrated circuit as described in claim 2 wherein said internal voltage bus is coupled to a power supply voltage of said integrated circuit.
6. An integrated circuit as described in claim 1 further comprising a plurality of metal oxide semiconductor transistors coupled to said body bias distribution circuit.
7. An integrated circuit as described in claim 6 wherein said plurality of metal oxide semiconductor transistors are coupled to said distribution circuit via respective body terminals.
8. An integrated circuit comprising:
a body bias distribution circuit operable to receive an externally applied voltage;
an internal voltage bus; and
a circuit component operable to isolate said internal voltage bus from said distribution circuit responsive to said externally applied voltage, wherein said externally applied voltage is substantially applied to said distribution circuit when said externally applied voltage is applied.
9. An integrated circuit as described in claim 8 wherein said circuit component is a resistor element.
10. An integrated circuit as described in claim 8 further comprising an external pin coupled to said pad, said external pin for coupling with said externally supplied voltage.
11. An integrated circuit as described in claim 8 wherein said internal voltage bus is coupled to a power supply voltage of said integrated circuit.
12. An integrated circuit as described in claim 8 further comprising a plurality of metal oxide semiconductor transistors coupled to said body bias distribution circuit.
13. An integrated circuit as described in claim 12 wherein said plurality of metal oxide semiconductor transistors are coupled to said distribution circuit via respective body terminals.
14. The integrated circuit of claim 8 wherein said circuit component comprises an n well region.
15. The integrated circuit of claim 14 wherein said circuit component forms a desired resistance between said internal voltage and said n well region.
16. A method of providing a body bias voltage in a semiconductor device comprising:
responsive to a coupling of an external body bias voltage to said semiconductor device, coupling said body bias voltage to body biasing wells of said semiconductor device.
17. The method of claim 16 further comprising:
responsive to an absence of said external body bias voltage, automatically supplying said body biasing wells of said semiconductor device with an internal voltage of said semiconductor device.
18. The method of claim 16 wherein said internal voltage is a power supply voltage for said semiconductor device.
19. The method of claim 16 wherein said internal voltage is a ground reference for said semiconductor device.