Method and apparatus for improving segmented memory addressing
View Patent ↗A method and apparatus for breaking complex X86 segment operations and segmented memory addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations.
1. A method comprising:
accessing stored context of present operating state of a processor to determine if a segment check operation can be eliminated when executing a memory access;
accessing said stored context to determine whether a base add operation can be eliminated when executing said memory access; and
issuing a base add instruction if said stored context does not indicate said base add operation can be eliminated when executing said memory access, wherein said base add instruction initiates said base add operation to generate a linear address for said memory address.
2. The method of claim 1 , further comprising:
determining during execution of said memory access that said base add operation can be eliminated.
3. The method of claim 2 , further comprising:
in response to said determining during execution, suppressing execution of said base add operation.
4. The method of claim 2 , wherein said determining during execution is based on said stored context.
5. The method of claim 1 , further comprising:
issuing a segment check instruction if said stored context does not indicate said segment check operation can be eliminated when executing said memory access, wherein said segment check instruction initiates said segment check operation; and
determining during execution of said memory access that said segment check operation can be eliminated.
6. The method of claim 5 , wherein said determining during execution is based on said stored context.
7. The method of claim 1 , wherein said stored context is stored by a register.
8. The method of claim 2 , further comprising:
eliminating said base add operation.
9. The method of claim 8 , wherein a compiler performs said eliminating said base add operation.
10. The method of claim 5 , further comprising:
eliminating said segment check operation.
11. The method of claim 10 , wherein a compiler performs said eliminating said segment check operation.
12. A method comprising:
issuing a sequence of instructions comprising memory accesses, said issuing the sequence of instructions comprising:
issuing base add instructions that initiate base add operations to generate linear addresses for respective ones of said memory accesses; and
performing an optimizing operation on said sequence of instructions, said performing comprises accessing stored context of present operating state of a processor.
13. The method of claim 12 , further comprising:
issuing segment check instructions that initiate segment check operations for respective ones of said memory accesses.
14. The method of claim 13 , wherein said performing the optimizing operation comprises eliminating at least one of said segment check instructions.
15. The method of claim 14 , wherein said performing the optimizing operation comprises eliminating at least one of said base add instructions.
16. The method of claim 12 , wherein said performing the optimizing operation comprises eliminating at least one of said base add instructions.
17. The method of claim 13 , wherein said performing the optimizing operation comprises eliminating at least one of said base add instructions.
18. The method of claim 14 , wherein said eliminating at least one of said segment check instructions is performed by a compiler.
19. The method of claim 15 , wherein said eliminating at least one of said base add instructions is performed by a compiler.
20. The method of claim 12 , wherein said stored context is stored by a register.