Inverting zipper repeater circuit

1. A repeater circuit comprising:

a circuit for accessing an input signal at an input terminal and producing an output signal at an output terminal analogous to said input signal, said circuit comprising:

a delay chain of inverters for producing first and second delayed versions of said input signal;

a holding subcircuit coupled to receive said first delayed version of said input signal and coupled to said output terminal of said repeater circuit;

a rising edge subcircuit comprising a first pulse generator to generate a rising output transition at said output terminal;

said first pulse generator accessing said input signal and said second delayed version of said input signal;

a falling edge subcircuit comprising a second pulse generator to generate a falling output transition at said output terminal;

said second pulse generator accessing said input signal and said second delayed version of said input signal;

a first latching circuit coupled to an output node of said first pulse generator and to said output terminal; and

a second latching circuit coupled to an output node of said second pulse generator and to said output terminal.

2. The repeater circuit of claim 1 , wherein said rising edge subcircuit generates a rising edge at said output terminal responsive to a falling edge of said input signal while maintaining a rising edge advantage over a falling edge in said repeater circuit.

3. The repeater circuit of claim 1 , wherein said falling edge subcircuit generates a falling edge at said output terminal responsive to a rising edge of said input signal while maintaining a falling edge advantage over a rising edge in said repeater circuit.

4. The repeater circuit of claim 1 , wherein said holding subcircuit further comprises:

a first inverter receiving said first delayed version of said input signal, said first inverter coupled in series with a second inverter and said output terminal, wherein said holding subcircuit maintains a state of said output terminal.

5. The repeater circuit of claim 1 , wherein:

said first pulse generator provides a first pulse signal that activates a first output transistor for generating a rising output transition at said output terminal; and wherein said second pulse generator provides a second pulse signal that activates a second output transistor for generating a falling output transition at said output terminal.

6. An inverting zipper repeater circuit comprising:

a holding subcircuit coupled to receive an input signal and coupled to an output terminal;

a delay chain of inverters coupled to receive said input signal;

a first pulse generator comprising said delay chain of inverters coupled to receive said input signal and for generating a rising output transition at said output terminal;

a first latching circuit coupled to an output node of said first pulse generator and to said output terminal;

a second pulse generator comprising said delay chain of inverters coupled to receive said input signal and for generating a falling output transition at said output terminal; and

a second latching circuit coupled to an output node of said second pulse generator and to said output terminal.

7. The inverting zipper repeater circuit of claim 6 , wherein said first pulse generator is responsive to a falling edge of said input signal.

8. The inverting zipper repeater circuit of claim 6 , wherein said second pulse generator is responsive to a rising edge of said input signal.

9. The inverting zipper repeater circuit of claim 6 , wherein said first pulse generator further comprises:

a NOR gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal;

an NFET coupled to an output node of said NOR gate, said NFET coupled to said first latching circuit and a first output transistor.

10. The inverting zipper repeater circuit of claim 9 , wherein said first latching circuit comprises:

a precharge circuit coupled to said output node of said first pulse generator; and

a half latch circuit coupled to said first output node.

11. The inverting zipper repeater circuit of claim 6 , wherein said second pulse generator further comprises:

a NAND gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal;

a PFET coupled to an output node of said NAND gate, said PFET coupled to said second latching circuit and a second output transistor.

12. The inverting zipper repeater circuit of claim 11 , wherein said second latching circuit comprises:

a precharge circuit coupled to said output node of said second pulse generator; and

a half latch circuit coupled to said second output node.

13. An inverting gain enhanced repeater circuit comprising:

a holding subcircuit coupled to receive a holding circuit input signal and coupled to an output terminal;

a delay chain of inverters coupled to receive an input signal;

a first pulse generator comprising said delay chain of inverters coupled to receive said input signal, said first pulse generator providing a first pulse signal that activates a first output transistor for generating a rising output transition at said output terminal;

wherein said first pulse generator comprises:

a NOR gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal, and an output node coupled to one static inverter with a skewed beta ratio and said first output transistor in series;

a second pulse generator comprising said delay chain of inverters that is coupled to receive said input signal, said second pulse generator providing a second pulse signal that activates a second output transistor for generating a falling output transition at said output terminal;

wherein said holding circuit input signal is delayed less than a delay of said delay chain.

14. The inverting gain enhanced repeater circuit of claim 13 , wherein said first pulse generator is responsive to a falling edge of said input signal to provide said first pulse signal.

15. The inverting gain enhanced repeater circuit of claim 13 , wherein said second pulse generator is responsive to a rising edge of said input signal to provide said second pulse signal.

16. The inverting gain enhanced repeater circuit of claim 13 , wherein said holding subcircuit further comprises:

a first inverter receiving said input signal, said first inverter coupled in series with a second inverter, a third inverter, and said output terminal, wherein said holding subcircuit maintains a state of said output terminal.

17. The inverting gain enhanced repeater circuit of claim 13 , wherein n-type field effect transistors (FETs) of said NOR gate are of a relatively smaller size compared to other p-type FETs in said NOR gate.

18. The inverting gain enhanced repeater circuit of claim 13 , wherein said second pulse generator comprises:

a NAND gate with input nodes coupled to receive a signal from said delay chain of inverters and said input signal, and an output node coupled to one static inverter with a skewed beta ratio and said second output transistor in series.

19. The inverting gain enhanced repeater circuit of claim 18 , wherein p-type field effect transistors (FETs) of said NAND gate are of a relatively smaller size compared to other n-type FETs in said NAND gate.

20. The inverting gain enhanced repeater circuit of claim 13 , wherein said input signal comprises a clock input signal, and wherein said output terminal outputs a clock output signal.