Systems and methods for integrated circuits comprising multiple body bias domains
View Patent ↗Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A first body biasing voltage is coupled to the first body bias domain, and a second body biasing voltage is coupled to the second body bias domain. The first and the second body biasing voltages are adjusted to achieve a desirable relative performance between the active semiconductor devices in the first and the second body bias domains.
1. A method of operating an integrated circuit comprising:
operating a delay locked loop circuit of said integrated circuit at a first tap granularity;
applying a body biasing voltage to said delay locked loop circuit; and
operating said delay locked loop circuit at a second tap granularity in response to said body biasing voltage.
2. A method according to claim 1 wherein said second tap granularity is less than said first tap granularity.
3. A method according to claim 1 further comprising accessing, at said delay locked loop circuit, a signal from other circuitry of said integrated circuit, wherein said other circuitry is independent of said body biasing voltage.
4. A method according to claim 1 wherein said integrated circuit comprises a microprocessor.
5. A method according to claim 3 wherein said delay locked loop circuit and said other circuitry operate at the same operating voltage.
6. A method according to claim 1 further comprising changing said body bias voltage.
7. An integrated circuit comprising a delay locked loop circuit disposed for receiving a body biasing voltage, wherein said body biasing voltage is operable to modify a tap granularity of said delay locked loop circuit.
8. An integrated circuit according to claim 7 wherein said body biasing voltage is separate from other circuitry of said integrated circuitry.
9. An integrated circuit according to claim 7 wherein an applied body bias voltage is operable to decrease a tap granularity of said delay locked loop circuit.
10. An integrated circuit according to claim 7 wherein said delay locked loop circuit is disposed to accept a plurality of body biasing voltage values to produce a plurality of tap granularities of said delay locked loop circuit.