Method and system for caching attribute data for matching attributes with physical addresses

1. A method comprising:

in response to a translation look aside buffer (TLB) miss, accessing an attribute cache to obtain at least one attribute corresponding to a physical address;

in response to a miss during said accessing the attribute cache, accessing logic to compute the at least one attribute for the physical address; and

storing the at least one attribute and the physical address within the attribute cache.

2. The method of claim 1 further comprising:

determining whether the attribute cache is configured for speculative loading.

3. The method of claim 1 further comprising: accessing the logic to compute a plurality of attributes for a plurality of speculative physical addresses.

4. The method of claim 1 further comprising:

storing the at least one attribute and the physical address within a translation look aside buffer (TLB).

5. The method of claim 4 , wherein the attribute cache comprises a greater number of entries than the TLB.

6. The method of claim 1 , wherein the attribute cache is configured to cache a first plurality of attributes that are time-consuming to obtain.

7. The method of claim 1 , wherein the attribute cache resides on a main data path of a virtual address to physical address translation circuitry.

8. A cache memory comprising:

an attribute cache operable to store attributes that correspond to physical addresses, wherein the attribute cache is accessed in response to a translation look aside buffer (TLB) miss; and

attribute logic operable to receive a physical address and operable to generate at least one attribute for the physical address to store in the attribute cache.

9. The cache memory of claim 8 , wherein the attribute cache is configured to support speculative attribute lookups to obtain a corresponding plurality of attribute entries.

10. The cache memory of claim 8 further comprising:

a page table operable to support an attribute lookup to obtain an attribute entry if the attribute entry is not stored in the attribute cache.

11. The cache memory of claim 8 , wherein the attribute cache includes a plurality of attribute entries that are indexed with physical addresses.

12. The cache memory of claim 8 , wherein at least one of the attributes is a translation bit that indicates whether a translation has been performed on a corresponding physical address.

13. The cache memory of claim 8 , wherein at least one of the attributes is a cache status bit that indicates a cache status of a corresponding physical address.

14. The cache memory of claim 8 , wherein the attribute cache is implemented as a parallel attribute cache.

15. The cache memory of claim 8 , wherein the attribute cache is implemented as a serial attribute cache.

16. The cache memory of claim 8 , wherein the attribute cache is implemented as a basic attribute cache.

17. A computer readable media comprising computer-executable instructions stored therein, the computer-executable instructions comprising:

instructions to access an attribute cache to obtain at least one attribute corresponding to a physical address in response to a translation look aside buffer (TLB) miss;

instructions to access logic to compute the at least one attribute for the physical address in response to a miss during said accessing the attribute cache; and

instructions to store the at least one attribute and the physical address within the attribute cache.

18. The computer readable media of claim 17 , wherein the computer-executable instructions further comprise:

instructions to access the logic to compute a plurality of attributes for a plurality of speculative physical addresses.

19. The computer readable media of claim 17 , wherein the attribute cache comprises a greater number of entries than a translation look aside buffer (TLB).

20. The computer readable media of claim 17 , wherein the attribute cache is configured to cache a first plurality of attributes that are time-consuming to obtain.