Enhanced clock signal flexible distribution system and method

1. An integrated circuit clock distribution system comprising:

a plurality of clocked components;

a clock grid mesh for distributing a clock signal to said clocked components; and

a diagonal offset clock signal distribution tree for distributing said clock signal to said clock grid mesh, wherein a diagonal offset of said diagonal offset clock signal distribution tree includes an orthogonal jog at a regular interval with respect to another orthogonal jog and said interval equals a separation in a relatively shorter distance between pads in a first orientation as compared to a relatively longer distance between pads in a second orientation, wherein paths of said diagonal offset clock signal distribution tree do not come back on one another between two adjacent pads, wherein said diagonal offset clock signal distribution tree and a power distribution grid are included in a top single metal layer of an integrated circuit.

2. An integrated circuit clock distribution system of claim 1 wherein opposing intermediate downstream branches of said diagonal offset clock signal distribution tree are diagonally offset on an intermediate upstream branch and said opposing intermediate down stream branches include said orthogonal jog.

3. An integrated circuit clock distribution system of claim 2 further comprising a pad for communicatively coupling external components to a power distribution grid, wherein said diagonal offset and said orthogonal jog are wider than said pad.

4. An integrated circuit clock distribution system of claim 1 wherein said top single metal layer includes a plurality of pads and a first orientation distance between pads is different from a second orientation distance between pads.

5. An integrated circuit clock distribution system of claim 1 wherein said diagonal offset clock signal distribution tree forms a uniform array of end points that said clocked components are tapped into.

6. An integrated circuit clock distribution system of claim 1 wherein said orthogonal jog is equal length to another orthogonal jog.

7. An integrated circuit clock distribution formation method:

forming a layer of clocked functional components in an integrated circuit;

depositing a clock grid mesh for distributing a clock signal to said clocked functional components; and

developing a diagonal offset clock signal distribution tree with an orthogonal jog for distributing said clock signal to said clock grid mesh, wherein said orthogonal jog is at a regular interval with respect to another orthogonal jog and said interval equals a separation in a relatively shorter distance between pads in a first orientation as compared to a relatively longer distance between pads in a second orientation, wherein paths of said diagonal offset clock signal distribution tree do not come back on one another between two adjacent pads, wherein said diagonal offset clock signal distribution tree and a power distribution grid are included in a top single metal layer of said integrated circuit.

8. An integrated circuit clock distribution formation method of claim 7 wherein said orthogonal jog is arranged in an orientation different from another orthogonal jog.

9. An integrated circuit clock distribution formation method of claim 7 further comprising shrinking down spacing between pads.

10. An integrated circuit clock distribution formation method of claim 7 wherein endpoints of said diagonal offset clock signal distribution tree are equidistant from a central clock source.

11. An integrated circuit clock distribution formation method of claim 7 wherein a diagonal offset and said orthogonal jog of said diagonal offset clock signal distribution tree avoid pads.

12. An integrated circuit clock distribution system comprising:

a plurality of clocked components;

a clock grid mesh for distributing a clock signal to said clocked components; and

a diagonal offset clock signal distribution tree for distributing said clock signal to said clock grid mesh, a first number of branch points in a first orientation are different from a second number of branch points in a second orientation, wherein a diagonal offset of said diagonal offset clock signal distribution tree includes an orthogonal jog at a regular interval with respect to another orthogonal jog and said interval equals a separation in a relatively shorter distance between pads in a first orientation as compared to a relatively longer distance between pads in a second orientation, wherein paths of said diagonal offset clock signal distribution tree do not come back on one another between two adjacent pads, wherein said diagonal offset clock signal distribution tree and a power distribution grid are included in a top single metal layer of said integrated circuit.

13. An integrated circuit clock distribution system of claim 12 wherein opposing intermediate downstream branches of said diagonal offset clock signal distribution tree are offset on an intermediate upstream branch.

14. An integrated circuit clock distribution system of claim 12 wherein said diagonal offset clock signal distribution tree includes buffers for driving said clock signal.

15. An integrated circuit clock distribution system of claim 14 wherein a first one of said buffers has a different driving capacity than a second one of said buffers.

16. An integrated circuit clock distribution system of claim 15 wherein said first one of said buffers is located at a diagonal intersection point of said diagonal offset clock signal distribution tree that goes in two directions and said second one of said buffers is located at a diagonal intersection point of said diagonal offset clock signal distribution tree that goes in one direction.

17. An integrated circuit clock distribution formation method:

forming a layer of clocked functional components in an integrated circuit;

depositing a clock grid mesh for distributing a clock signal to said clocked functional components; and

developing a diagonal offset clock signal distribution tree for distributing said clock signal to said clock grid mesh, wherein said diagonal offset clock signal distribution tree covers a rectangular area, wherein a diagonal offset of said diagonal offset clock signal distribution tree includes an orthogonal jog at a regular interval with respect to another orthogonal jog and said interval equals a separation in a relatively shorter distance between pads in a first orientation as compared to a relatively longer distance between pads in a second orientation, wherein paths of said diagonal offset clock signal distribution tree do not come back on one another between two adjacent pads, wherein said diagonal offset clock signal distribution tree and a power distribution grid are included in a top single metal layer of said integrated circuit.

18. An integrated circuit clock distribution formation method of claim 17 further comprising inserting a first size buffer in said diagonal offset clock signal distribution tree at a symmetrical intersection point and a second size buffer in said diagonal offset clock signal distribution tree at an asymmetrical intersection point.

19. An integrated circuit clock distribution formation method of claim 17 wherein a first endpoint of said diagonal offset clock signal distribution tree and a second endpoint of said diagonal offset clock signal distribution tree are equidistant from a central clock source.