Setting a flag bit to defer event handling to a safe point in an instruction stream
View Patent ↗Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.
1. A computer-readable storage device having stored thereon, computer-executable instructions that, responsive to execution by a computing device, cause the computing device to perform operations comprising:
during execution of a stream of instructions demarcated by a first commit instruction and a second commit instruction and without an intervening commit instruction after the first commit instruction and before the second commit instruction, identifying an event to be handled, wherein the event is associated with a first instruction in the stream;
setting a flag bit to indicate deferred handling of the event; and
generating an exception corresponding to the event if the flag bit is set, wherein the exception causes the event to be handled at the first commit instruction if a rollback operation occurs during the execution of the stream of instructions and otherwise at the second commit instruction.
2. The computer-readable storage device of claim 1 wherein there are a plurality of flag bits and a corresponding number of instructions, wherein one of the flag bits is set for each event identified during execution of the stream, wherein an exception is generated for each of the flag bits that is set.
3. The computer-readable storage device of claim 1 wherein the event is a trap.
4. The computer-readable storage device of claim 1 wherein the stream comprises native instructions translated from non-native instructions.
5. The computer-readable storage device of claim 4 wherein the non-native instructions comprise x86 instructions and wherein the native instructions comprise Very Long Instruction Word (VLIW) instructions.
6. The computer-readable storage device of claim 1 wherein two flag bits are used for indicating that the event is to be handled, wherein one of the two flag bits is for indicating the exception is to be handled at the first commit instruction and the other of the two flag bits is for indicating the exception is to be handled at the second commit instruction.
7. The computer-readable storage device of claim 1 wherein the operations further comprise clearing the flag bit.
8. A computer system comprising:
a processor; and
memory coupled to the processor and having stored therein instructions that, if executed by the computer system, cause the computer system to perform operations comprising:
during execution of a stream comprising multiple instructions, wherein the stream is demarcated by a first commit instruction and a second commit instruction and wherein the first and second commit instructions comprise consecutive commit instructions without an intervening commit instruction, identifying an event to be handled, wherein the event is associated with a first instruction of the multiple instructions;
setting a flag bit to indicate that the event is identified but handling of the event is to be deferred; and
generating an exception corresponding to the event if the flag bit is set, wherein the exception causes the event to be handled at the second commit instruction unless a rollback operation occurs during the execution of the stream and at the first commit instruction if the rollback operation occurs.
9. The computer system of claim 8 wherein there are a plurality of flag bits and a corresponding number of instructions, wherein one of the flag bits is set for each event identified during execution of the stream, wherein an exception is generated for each of the flag bits that is set.
10. The computer system of claim 8 wherein the event is a trap.
11. The computer system of claim 8 wherein the stream of the multiple instructions comprises native instructions translated from non-native instructions.
12. The computer system of claim 11 wherein the non-native instructions comprise x86 instructions and wherein the native instructions comprise Very Long Instruction Word (VLIW) instructions.
13. The computer system of claim 8 wherein two flag bits are used for indicating that the event is to be handled, wherein one of the two flag bits is for indicating the exception is to be handled at the first commit instruction and the other of the two flag bits is for indicating the exception is to be handled at the second commit instruction.
14. The computer system of claim 8 wherein the operations further comprise clearing the flag bit.