Structure for spanning gap in body-bias voltage routing structure

1. A semiconductor device having a surface, said device comprising:

a plurality of conductive sub-surface regions of a first conductivity each formed beneath said surface, wherein said plurality of conductive sub-surface regions form a sub-surface structure operable to route a body-bias voltage, and wherein said sub-surface structure has a perimeter;

an isolation structure formed within said perimeter of said sub-surface structure wherein said isolation structure creates a gap in said sub-surface structure; and

at least one metal structure formed above said surface, wherein said at least one metal structure spans said gap and is coupled to said sub-surface structure via a plurality of tap contacts.

2. The semiconductor device of claim 1 , wherein each conductive sub-surface region has an N-type doping.

3. The semiconductor device of claim 1 , wherein each conductive sub-surface region has a P-type doping.

4. The semiconductor device of claim 1 , wherein each conductive sub-surface region has a strip shape.

5. The semiconductor device of claim 1 , wherein said metal structure has a metal wire shape.

6. The semiconductor device of claim 1 , further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said metal structure that overlaps said sub-surface structure, wherein each of said plurality of second conductive sub-surface regions has a continuous sub-surface layer shape.

7. A semiconductor device having a surface, said device comprising:

a first plurality of conductive sub-surface regions of a first conductivity each formed beneath said surface, wherein said first plurality of conductive sub-surface regions form a first sub-surface structure operable to route a body-bias voltage;

a second plurality of conductive sub-surface regions of said first conductivity each formed beneath said surface, wherein said second plurality of conductive sub-surface regions form a second sub-surface structure operable to route said body-bias voltage;

an isolation structure formed between said first sub-surface structure and said second sub-surface structure, wherein said isolation structure creates a gap between said first sub-surface structure and said second sub-surface structure; and

at least one metal structure formed above said surface, wherein said metal structure spans said gap and is coupled to said first sub-surface structure and said second sub-surface structure via a plurality of tap contacts.

8. The semiconductor device of claim 7 , wherein each conductive sub-surface region has an N-type doping.

9. The semiconductor device of claim 7 , wherein each conductive sub-surface region has a P-type doping.

10. The semiconductor device of claim 7 , wherein each conductive sub-surface region has a strip shape.

11. The semiconductor device of claim 7 , wherein said metal structure has a metal wire shape.

12. The semiconductor device of claim 7 , further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said metal structure that overlaps said first and second sub-surface structures, wherein each of said plurality second conductive sub-surface regions has a continuous sub-surface layer shape.

13. A semiconductor device having a surface, said device comprising:

a plurality of conductive sub-surface regions of a first conductivity each formed beneath said surface, wherein said conductive sub-surface regions form a sub-surface structure operable to route a body-bias voltage, and wherein said sub-surface structure has a perimeter;

an isolation structure formed within said perimeter of said sub-surface structure wherein said isolation structure creates a gap in said sub-surface structure; and

at least one structure that spans said gap and is coupled to said sub-surface structure.

14. The semiconductor device of claim 13 , wherein each conductive sub-surface region has an N-type doping.

15. The semiconductor device of claim 13 , wherein each conductive sub-surface region has a P-type doping.

16. The semiconductor device of claim 13 , wherein each conductive sub-surface region has a strip shape.

17. The semiconductor device of claim 13 , wherein said structure is a polysilicon wire.

18. The semiconductor device of claim 13 , wherein said structure is a diffusion wire.

19. The semiconductor device of claim 13 , wherein said structure is a silicide wire.

20. The semiconductor device of claim 13 , further comprising a plurality of second conductive sub-surface regions of said first conductivity each formed under each portion of said structure that overlaps said sub-surface structure, wherein each of said plurality of second conductive sub-surface regions has a continuous sub-surface layer shape.

21. The semiconductor device of claim 13 , wherein said isolation structure divides said sub-surface structure into a first portion and a second portion.

22. The semiconductor device of claim 1 , wherein said sub-surface structure is selected from the group consisting of an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure.

23. The semiconductor device of claim 7 , wherein said first sub-surface structure is selected from the group consisting of a first axial sub-surface mesh structure, a first diagonal sub-surface strip structure, and a first axial sub-surface strip structure.

24. The semiconductor device of claim 23 , wherein said second sub-surface structure is selected from the group consisting of a second axial sub-surface mesh structure, a second diagonal sub-surface strip structure, and a second axial sub-surface strip structure.

25. The semiconductor device of claim 13 , wherein said sub-surface structure is selected from the group consisting of an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure.